A 2.5 GHz, 87-fs Step, Temperature-and-Voltage-Tolerant 6-bit Digital-to-Time Converter in 28nm CMOS
Abstract
This paper presents a temperature-and-voltage-tolerant 2.5GHz 6-bit digital-to-time converter (DTC) with an 87-fs resolution. The capacitor-DAC (CDAC) based DTC can achieve high resolution and linearity, but typical DTC structures suffer from performance degradation due to temperature and voltage variations. To address this issue, we implement a replica feedback loop consisting of a regulated constant-slope DTC, which effectively maintains the delay of the DTC even as temperature and voltage conditions fluctuate. Additionally, an on-chip histogram counter accurately measures on-chip delays. The proposed DTC in this paper is fabricated in a 28-nm CMOS process, with the core occupying an area of 0.0129 mm2. It operates at 2.5 GHz with a 0.9 V supply voltage, consuming only 0.82 mW. Measured results demonstrate that the full-scale range changes for 125 °C temperature variation and for 200mV supply variation are reduced by 7.2x and 1.9x, respectively.