A Cell-Based Implementation of ARM Cortex-M0 SoC

Hye-Seung Sun; In-Shin Cho

doi:10.23075/jicas.2024.10.4.008

Hye-Seung Sun Korea Polytechnics
In-Shin Cho Integrated Circuit Design Education Center, Korea Advanced Institute of Science and Technology

DOI: https://doi.org/10.23075/jicas.2024.10.4.008

Keywords: ARM, Cortex-M0, Cell based Digital ASIC, Platform, Samsung 28nm, Hierarchical Design

Abstract

For academic research purposes, ARM provided its SoC platform. This study presents the methods and results of implementing the Cortex-M0 as a chip. The behavioral memory was replaced with the foundry's memory, and the design was modified to allow software to be written externally to the chip at any time. During chip implementation, IDEC's guidelines were followed, utilizing as many tools as possible to increase the chip's functionality. The fabricated Cortex-M0 chip was mounted on a test board and was verified to work well in conjunction with the software. A hierarchical approach was adopted during the chip's implementation, with efforts made to minimize its size and facilitate its use as a platform. In this study, Samsung 28nm LPP process was applied

Author Biographies

Hye-Seung Sun, Korea Polytechnics

Hye-Seung Sun received his B.S. degree in information and communication engineering from Hanbat National University, Daejeon, Korea, in 2007 and received the M.S. degrees in computer engineering in from Hanbat National University, Daejeon, Korea, in 2009.

His research interest includes digital ASIC design flow. In particular, he is currently conducting the research on low power IC design for ARM Cortex SoC Platform.

In-Shin Cho, Integrated Circuit Design Education Center, Korea Advanced Institute of Science and Technology

In-Shin Cho received his B.S. degree in information and communication engineering from Hanbat National University, Daejeon, Korea, in 2005 and received the M.S. degrees in computer engineering in from Hanbat National University, Daejeon, Korea, in 2007.

His research interest includes analog ASIC design flow. In particular, he is currently conducting the research on low-power IC design.

A Cell-Based Implementation of ARM Cortex-M0 SoC

Abstract

Author Biographies

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