A Low-Power, Highly Linear Sub-GHz Receiver Front-End with a Voltage Follower-Based 4th-Order Channel Selection Filter

Deok-Young  Kim; Jong-Won  Park; Yaehoon Roh; Gyeore Lee; Donggu Im

doi:10.23075/jicas.2024.10.4.005

Deok-Young Kim Department of Electronic Engineering, Jeonbuk National University
Jong-Won Park Department of Electronic Engineering, Jeonbuk National University
Yaehoon Roh Department of Electronic Engineering, Jeonbuk National University
Gyeore Lee Department of Electronic Engineering, Jeonbuk National University
Donggu Im Department of Electronic Engineering, Jeonbuk National University

DOI: https://doi.org/10.23075/jicas.2024.10.4.005

Keywords: CMOS, channel selection filter, flipped voltage follower, inverter, low-pass filer, LPWAN, single-to-differential LNA, sub-GHz, super source follower

Abstract

A low-power highly linear sub-GHz receiver front-end employing a voltage follower based 4^th-order channel selection filter is proposed for low-power wide-area network (LPWAN) IoT applications. It consists of wideband single-to-differential (S-to-D) low noise amplifier (LNA), in-phase/quadrature (I/Q) passive mixer, and voltage-follower based 4^th-order channel selection filter. The proposed S-to-D LNA is designed on the basis of two cascaded inverters for S-to-D conversion and the correction amplifier to compensate the amplitude and phase imbalance and implement feedback. It shows relatively high gain, low noise, high linearity with simple hardware configuration and low power consumption The proposed channel selection filter is implemented using the more advanced source follower combining the flipped voltage follower (FVF) and super source follower (SSF), and the low power technique for implementing high-order filter is newly proposed in the design of channel selection filter. Eventually, the 4^th-order filter topology is devised without noise figure (NF) degradation compared to the 2^nd-order filter. In the simulation, the proposed receiver designed with a 130-nm CMOS technology shows the conversion gain of about 30 dB and double-sideband NF (NF_DSB) of 3.2 dB at 500 MHz operating frequency. The simulated output-referred third-order intercept point (OIP3) of the designed receiver ranges from +5 dBm to +7 dBm in sub-GHz band. The total power consumption of the receiver is 9.6 mW from a 1.2 V supply voltage.

Author Biographies

Deok-Young Kim, Department of Electronic Engineering, Jeonbuk National University

Deok-Young Kim received the B.S. degree from the Division of Electronic Engineering at Jeonbuk National University (JBNU), Jeonju, South Korea, in 2024, where he is currently pursuing the M.S. degree. His research during M.S. course has focused on low-power IoT CMOS front-end circuit design, such as wideband low-noise amplifiers (LNAs).

Jong-Won Park, Department of Electronic Engineering, Jeonbuk National University

Jong-Won Park received the B.S. degree from the Division of Electronic Engineering at Jeonbuk National University (JBNU), Jeonju, South Korea, in 2024, where he is currently pursuing the M.S. degree. His research during M.S. course has focused on low-power IoT CMOS front-end circuit design, such as highly linear RF filters.

Yaehoon Roh, Department of Electronic Engineering, Jeonbuk National University

Yaehoon Roh received the B.S. degree from the Division of Electronic Engineering at Jeonbuk National University (JBNU), Jeonju, South Korea, in 2023, where he is currently pursuing the M.S. degree. His research during M.S. course has focused on time delay cells such as reconfigurable sub-GHz inductor-less time delay cells in CMOS.

Gyeore Lee, Department of Electronic Engineering, Jeonbuk National University

Gyeore Lee received the B.S. and M.S. degrees from the Division of Electronic Engineering, Jeonbuk National University (JBNU), Jeonju, South Korea, in 2021, and 2023, respectively, where he is currently pursuing the Ph.D. degree with the Division of Electronic Engineering. His research during Ph.D. course has focused on the RF switches, touch sensors ROICs and spectrum sensing based on mixer first.

Donggu Im, Department of Electronic Engineering, Jeonbuk National University

Donggu Im received the B.S., M.S., and Ph.D. degrees in electrical engineering and computer science from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2004, 2006, and 2012, respectively. From 2006 to 2009, he was an Associate Research Engineer with LG Electronics, Seoul, Korea, where he was involved in the development of universal analog and digital TV receiver ICs. From 2012 to 2013, he was a Post-Doctoral Researcher with KAIST, where he was involved in the development of the first RF SOI CMOS technology in Korea with SOI business team in National NanoFab Center (NNFC), Daejeon, Korea. In 2013, he joined the Texas Analog Center of Excellence (TxACE), Department of Electrical Engineering, University of Texas at Dallas, as a Research Associate, where he developed ultra-low-power CMOS radios with adaptive impedance tuning circuits. In 2014, he joined the Division of Electronic Engineering, Jeonbuk National University, Jeollabuk-do, Korea, and is now a professor. His research interests are CMOS analog/RF/mm-wave ICs and system design.