A DRAM-Based Process-in-Memory Using Data Redundancy and Differential Bit-Line Computation
Keywords:
DRAM-Based Process-In-Memory, Multiply-and-accumulate (MAC), Multiple word-line activation
Abstract
This paper presents a novel DRAM-IMC structure achieving high throughput without altering the existing cell configuration. Multiple WL activations are utilized to enhance the throughput of MAC operations. The issue of data destruction during simultaneous WL activations is addressed by employing the adjacent MAT and differential operation of the sense amplifier. Moreover, the problem arising from non-ideality in WL switches is alleviated through the differential bit-line computation operation. Consequently, an accuracy of 99.01% was achieved on the MNIST dataset.
Published
2024-01-01
How to Cite
Yoon, H., Kim, D., Lee, G., & Cho, S. (2024). A DRAM-Based Process-in-Memory Using Data Redundancy and Differential Bit-Line Computation. Journal of Integrated Circuits and Systems, 10(1). https://doi.org/10.23075/jicas.2024.10.1.002
Issue
Section
Articles