A DRAM-Based Process-in-Memory Using Data Redundancy and Differential Bit-Line Computation

  • Hyein Yoon Samsung Electronics
  • Donghwan Kim Korea Advanced Institute of Science and Technology
  • Giwoo Lee Korea Advanced Institute of Science and Technology
  • SeongHwan Cho Korea Advanced Institute of Science and Technology https://orcid.org/0000-0001-7938-2694
Keywords: DRAM-Based Process-In-Memory, Multiply-and-accumulate (MAC), Multiple word-line activation

Abstract

This paper presents a novel DRAM-IMC structure achieving high throughput without altering the existing cell configuration. Multiple WL activations are utilized to enhance the throughput of MAC operations. The issue of data destruction during simultaneous WL activations is addressed by employing the adjacent MAT and differential operation of the sense amplifier. Moreover, the problem arising from non-ideality in WL switches is alleviated through the differential bit-line computation operation. Consequently, an accuracy of 99.01% was achieved on the MNIST dataset.

Author Biographies

Hyein Yoon, Samsung Electronics

Hyein Yoon received the B.S. degrees in electrical engineering from Korea University, Seoul, South Korea, in 2020, and M.S degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2022. Her research interest includes DRAM processor in memory for machine learning. Especially, she is currently conducting the research on smart scheduler in NAND flash memory in Samsung Electronics.

Donghwan Kim, Korea Advanced Institute of Science and Technology

Donghwan Kim received the B.S. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2019. He is currently pursuing the integrated master’s and doctoral degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His research interest includes memory IC and PIM for area efficient application.

Giwoo Lee, Korea Advanced Institute of Science and Technology

Giwoo Lee received the B.S. degrees in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 2021. He is currently pursuing the integrated master’s and doctoral degree in electrical engineering from Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His research interest includes memory IC and PIM for low power application.

SeongHwan Cho, Korea Advanced Institute of Science and Technology

SeongHwan Cho received the B.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea, in 1995, and the M.S. and Ph.D. degrees in EECS from MIT, Cambridge, MA, USA, in 1997 and 2002, respectively.
In 2002, he joined Engim, Inc. Acton, MA, USA, where he was involved in data converters and phased-locked loop (PLL) design for IEEE 802.11abg WLANs. Since 2004, he has been with the School of EE, KAIST, where he is currently a Professor and the Department Head of semiconductor system engineering. He was with Marvell Inc., Santa Clara, CA, USA, from 2011 to 2012, and Google, London, U.K., from 2016 to 2017, as the Research Scientist. His research interests include analog and mixed-signal circuits for high-speed communication, low-power sensors, memory, and machine learning.
Prof. Cho was a co-recipient of the 2009 IEEE Circuits and System Society Guillemin-Cauer Best Paper Award and the 2012 ISSCC Takuo Sugano Award for Outstanding Far-East Paper. He has twice received Outstanding Lecturer Award from KAIST. He has served on the Technical Program Committee on several IEEE conferences, including ISSCC, Symposium on VLSI and A-SSCC. He has served as an Associate Editor for IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, and Distinguished Lecturer of the IEEE Solid-State Circuits Society.

Homepage: https://ccs.kaist.ac.kr/

Published
2024-01-01
How to Cite
Yoon, H., Kim, D., Lee, G., & Cho, S. (2024). A DRAM-Based Process-in-Memory Using Data Redundancy and Differential Bit-Line Computation. Journal of Integrated Circuits and Systems, 10(1). https://doi.org/10.23075/jicas.2024.10.1.002
Section
Articles