A Low-jitter Ring-DCO-Based Digital PLL  Using P/I-Gain Co-Optimization and Optimally Spaced TDC for Flicker-Noise Reduction

Chanwoong Hwang; Hangi Park; Yongsun Lee; Taeho Seong; Jaehyouk Choi

doi:10.23075/jicas.2023.9.4.008

Chanwoong Hwang Korea Advanced Institute of Science and Technology / Seoul National University
Hangi Park Korea Advanced Institute of Science and Technology / Seoul National University
Yongsun Lee Samsung Electronics
Taeho Seong Qualcomm
Jaehyouk Choi Seoul National University

DOI: https://doi.org/10.23075/jicas.2023.9.4.008

Keywords: ring digitally-controlled-oscillator, digital phase-locked-loop, time-to-digital-conveter, digital-loop filter, flicker noise, thermal noise

Abstract

This work presents a ring-oscillator-based digital PLL (RO-DPLL). To achieve low jitter, the proposed RO-DPLL used calibration techniques to optimize the gain of the Proportional-path (P-path) and Integral-path (I-path) in the digital-loop-filter (DLF) simultaneously. Since the effect of flicker noise increases as the frequency increases, the frequency drift of the RO-DPLL becomes more severe in the operation of the RO-DPLL. Thus, it is critical to calibrate the gain of the I-path to an optimal value because I-path of DLF compensates for the frequency error of the PLL. Moreover, the optimally-spaced time-to-digital-converter (OS-TDC) with the threshold calibrator provides sufficient information, supporting the efficient operation of the calibrators. Due to the use of the P/I-path co-optimization (PICO and OS-TDC with calibrator, the proposed RO-DPLL achieved 343 fs of the rms jitter and –65dBc of the reference spur. And, its FoM_jitter,N was –258.5 dBc, comparable to the state-of-the-art RO-based analog PLLs.

Author Biographies

Chanwoong Hwang, Korea Advanced Institute of Science and Technology / Seoul National University

Chanwoong Hwang (Graduate Student Member, IEEE) was born in Ulsan, South Korea, in 1994. He received the B.S. degree (summa cum laude) in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2019. He is currently pursuing the M.S/Ph.D. degree with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His research interest includes CMOS analog/mixed integrated circuit (IC) designs, especially high-speed clock/frequency generation systems. Mr. Hwang received two Silver Prizes of the Samsung Human-Tech Paper Award in Circuit Design hosted by Samsung Electronics in 2020 and 2021.

Hangi Park, Korea Advanced Institute of Science and Technology / Seoul National University

Hangi Park (Graduate Student Member, IEEE) was born in Anseong, South Korea, in 1997. He received the B.S. degree in engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2019. He is currently pursuing the M.S/Ph.D. degree with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His research interests include CMOS analog/mixed integrated circuit (IC) designs, especially highspeed clock/frequency generation systems. Mr. Park received the Silver Prize of the Samsung HumanTech Paper Award in Circuit Design hosted by Samsung Electronics in 2021.

Yongsun Lee, Samsung Electronics

Yongsun Lee (Member, IEEE) was born in Incheon, South Korea, in 1991. He received the B.S., ahd Ph. D. degrees in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2014 and 2020, respectively. Since 2020, he has been with Samsung Electronics Corporation, Hwaseong, South
Korea, where he is involved in the design of high-speed SerDes transceivers. His current research interests include clock/frequency generation systems and clock and data recovery for emerging data communication systems. Dr. Lee received two Silver Prizes (2020 and 2019) and three Bronze Prizes (2019, 2018, and 2017) in the Samsung Human-Tech Paper Award in Circuit Design hosted by Samsung Electronics.

Taeho Seong, Qualcomm

Taeho Seong (Member, IEEE) was born in South Korea, in 1992. He received the B.S. and Ph.D. degrees in electrical engineering from the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, in 2015 and 2022, respectively.
In 2022, he joined the Qualcomm RF IC Design Group, where he is currently a Senior Engineer. At Qualcomm, he focuses on frequency synthesizer for wireless transceivers. His research interests include analog/mixed integrated circuit (IC) designs, especially innovative clock generation circuits
Dr. Seong received three silver prizes (2021, 2020, and 2019) and one bronze prize in 2018 in the Samsung Human-Tech Paper Award in Circuit Design hosted by Samsung Electronics.

Jaehyouk Choi, Seoul National University

Jaehyouk Choi (S’06–M’11) (Senior Member, IEEE) was born in Seoul, South Korea, in 1980. He received the B.S. degree (summa cum laude) in electrical engineering from Seoul National University, Seoul, in 2003 and the M.S. and Ph.D. degrees in electrical and computer engineering from the Georgia Institute of Technology, Atlanta, GA, USA, in 2008 and 2010, respectively. From 2010 to 2011, he was with Qualcomm, Inc., San Diego, CA, USA, where he was involved in designing multi-standard cellular transceivers. In 2012, he joined the Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, as a Faculty Member. Since 2019, he has been an Associate Professor with the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea. His research interests include low-power and high-performance analog, mixed-signal, and RF integrated circuits for emerging wireless/wired standards. Dr. Choi has been a TPC Member of the IEEE International Solid-State Circuits Conference (ISSCC) since 2017, the IEEE European Solid-State Circuits Conference (ESSCIRC) since 2016, and the IEEE Asian Solid-State Circuits Conference (ASSCC) since 2021. He was a Distinguished Lecturer (DL) of the Solid-State Circuits Society (SSCS) from 2020 to 2021. He is ISSCC TPC Far-East Regional Vice Chair for ISSCC 2024, and has served as an Associate Editor of IEEE Journal of SolidState Circuits (JSSC). He was a recipient of IEEE-IEIE Joint Award: Young Engineer of the Year 2020.

Homepage: https://icsl.snu.ac.kr