Logic Operation Implementation Method with Single-Level Cell NAND Flash
Abstract
With the advent of the big data era, the memory wall has become a dominant issue in computer hardware design. To overcome the memory wall issue, processing-in-memory (PIM) technology has been actively researched with various types of memory devices including static random-access memory (SRAM), dynamic random-access memory (DRAM), resistive random-access memory (RRAM) and charge trap flash (CTF). However, a logic operation implementation methodology for single-level cell (SLC) NAND flash, has yet to be investigated. This paper proposes and validates a method for implementing logic operations on SLC NAND flash. The proposed logic operation implementation method was demonstrated by Sentaurus TCAD mixed-mode simulations.