High-Throughput FPGA Implementation of Sliding DCT using Look-Ahead Pipelining

Abstract

The Discrete Cosine Transform (DCT) is often applied in a sliding window setting. While sliding DCT (SDCT) algorithms take advantage of the computational redundancy inherent from the overlap between consequent processing windows, the recursive computation nature imposes a fundamental limit on realizable throughput. This study presents a high-throughput FPGA implementation of the SDCT algorithm using look-ahead pipelining. A look-ahead transformation of degree two is applied to the original SDCT recursion formula resulting in a threefold reduction of the iteration bound. The resulting maximum clock frequency on a Xilinx FPGA device is increased 2.1x (from 58.4 MHz to 123.4 MHz) by carefully retiming the look-ahead pipeline registers and inserting additional pipeline registers in feed-forward cutsets of the signal-flow graph.