A 6Gb/s Transceiver Design with Phase-Difference Modulation Signaling for Multi-drop DRAM Interface

Abstract

In this paper, we presented the application of phase-difference modulation (PDM) signaling for extending the drop count in the multi-drop DRAM interface. Because PDM signaling does not require equalization techniques to suppress the reflective inter-symbol interferences (ISIs), PDM transceiver can extend the number of drop counts without increasing the design cost. With PDM signaling, we implemented the two amplifiers, which make the design complexity of the clock recovery circuit simple: the clock recovery circuit is a simple interpolator. The proposed PDM transceiver was fabricated in 65 nm CMOS technology and verified the performance by simulations. To verify the performance of the PDM signaling, we compared the simulated 6 Gb/s eye diagram in the multi-drop channel with the NRZ signaling. The simulated vertical and horizontal eye sizes in PDM signaling were increased to 60.5 mV and 63.7 ps, respectively; but the simulated eye was closed in NRZ signaling. Therefore, with PDM signaling, the multi-drop memory interfaces with high capacity are feasible without increasing the power and hardware cost.