Reverse Engineering for Xilinx FPGA Chips using ISE Design Tools

So Yeon  Choi; Ji Woon  Park; Ho Young Yoo

doi:10.23075/jicas.2020.6.1.003

So Yeon Choi Chungnam National University
Ji Woon Park Chungnam National University
Ho Young Yoo Chungnam National University

DOI: https://doi.org/10.23075/jicas.2020.6.1.003

Keywords: ISE Design Tools, Programmable logic points, Programmable interconnect points, Reverse Engineering, Xilinx FPGA

Abstract

SRAM-based field-programmable gate arrays (FPGAs) are used in several industries. However, the SRAM-based FPGA is volatile and requires additional nonvolatile memory to store the netlist information of the circuit outside the FPGA as a bitstream file. When the FPGA is powered, the bitstream file is transferred from the external nonvolatile memory to the FPGA. If the bitstream is corrupted, it will cause a fatal problem in the circuit. The process of converting a bitstream into a file that contains the internal netlist information of the FPGA is called reverse engineering. In this paper, we described the process of reverse engineering with mapping table based on ISE design tools in details. To generate the mapping table, we developed XDL generator and RBT comparator which are operated with the input files, XDL, XDLRC and bitstream files. After that, the bitstream in external memory can be recovered the XDL file using mapping table. The reverse engineering tool with mapping table can be recovered 88% internal circuit compared with original circuit.

Author Biographies

So Yeon Choi, Chungnam National University

So Yeon Choi received the B.S. degree in electronics engineering from Chungnam National University, Daejeon, Korea, in 2018. Her main research interests include VLSI for error correction codes and FPGA reconfiguration.

Ji Woon Park, Chungnam National University

Ji Woon Park is working toward the B.S. degree in electrical engineering from Chungnam National University, Daejeon, Korea, in 2020. His main interests are VLSI for error correction codes and FPGA reconfiguration.

Ho Young Yoo, Chungnam National University

Ho Young Yoo received the B.S. degree in electrical & electronics engineering from Yonsei University, Seoul, Korea, in 2010. He received the M.S. and Ph.D. degree in electronic engineering from KAIST in 2012 and 2016. Since 2016, he has been with the department of Electronics Engineering, Chungnam National University, Daejeon, Korea, where he is now an Assistant Professor. His research interests include VLSI for 5G communication systems and VLSI for Machine Learning Accelerators.

Homepage : https://cas.cnu.ac.kr/