Reverse Engineering for Xilinx FPGA Chips using ISE Design Tools

So Yeon  Choi; Ji Woon  Park; Ho Young Yoo

doi:10.23075/jicas.2020.6.1.003

So Yeon Choi Chungnam National University
Ji Woon Park Chungnam National University
Ho Young Yoo Chungnam National University

DOI: https://doi.org/10.23075/jicas.2020.6.1.003

Keywords: ISE Design Tools, Programmable logic points, Programmable interconnect points, Reverse Engineering, Xilinx FPGA

Abstract

SRAM-based Field Programmable Gate Arrays (FPGAs) are more widely used compared to Flash-based and anti-fuse based FPGAs in various industries. One disadvantage of the SRAM-based FPGA is that SRAM is natively volatile and thus it requires additional nonvolatile memory to store the netlist information of the circuit outside the FPGA. When the FPGA is powered on, the bitstream file is transferred from the external nonvolatile memory to the SRAM-based FPGA. The secure issues arise if the bitstream is modified or corrupted by attacker resulting in a fatal problem in the circuit. Therefore, reverse engineering that converting a bitstream into an internal netlist is necessary to find such harmful modification. In this paper, we describe the overall process of reverse engineering based on ISE design tools in details. According to the experimental results, the proposed reverse engineering tool can recover 88% internal circuit as for the example of 64-bit LFSR design.

Author Biographies

So Yeon Choi, Chungnam National University

So Yeon Choi received the B.S. degree in electronics engineering from Chungnam National University, Daejeon, Korea, in 2018. Her main research interests include VLSI for error correction codes and FPGA reconfiguration.

Ji Woon Park, Chungnam National University

Ji Woon Park is working toward the B.S. degree in electrical engineering from Chungnam National University, Daejeon, Korea, in 2020. His main interests are VLSI for error correction codes and FPGA reconfiguration.

Ho Young Yoo, Chungnam National University

Ho Young Yoo received the B.S. degree in electrical & electronics engineering from Yonsei University, Seoul, Korea, in 2010. He received the M.S. and Ph.D. degree in electronic engineering from KAIST in 2012 and 2016. Since 2016, he has been with the department of Electronics Engineering, Chungnam National University, Daejeon, Korea, where he is now an Assistant Professor. His research interests include VLSI for 5G communication systems and VLSI for Machine Learning Accelerators.

Homepage : https://cas.cnu.ac.kr/