Journal of Integrated Circuits and Systems

On-Chip Battery EIS Analog Frontend for Embedded Battery Management System

2025-10-01T23:01:25+09:00

Electrochemical Impedance Spectroscopy (EIS) is an emerging diagnostic technique for battery characterization. Conventional EIS systems utilize external instrumentation assemblies, limiting their practicality for real-time monitoring applications in electric vehicles (EVs) and energy storage systems (ESS) that require timely impedance data acquisition for operational battery management decisions. This paper presents a novel integrated circuit conforming to AEC-Q100 Grade 1 specifications, operating reliably from -40°C to 125°C, with four measurement channels. The architecture incorporates an on-chip high-pass filter (HPF) for impedance measurement and a zero-temperature-coefficient (ZTC) power supply that maintains stability across the operational temperature range. This integration eliminates the need for external RC components at the HPF stage, thereby reducing system complexity and cost. Post-layout simulation results demonstrate measurement accuracy across various operating conditions. The presented solution enables real-time battery diagnostics and predictive maintenance capabilities, enhancing safety, reliability, and operational lifespan for next-generation embedded battery management systems.

A Single-Ended NRZ Transceiver in 28-nm CMOS Process with Power-Isolated LVSTL Driver and 3-Stage Sampler for Low-Power Memory Interfaces

2025-10-01T23:02:40+09:00

This paper presents a low-power, high-speed nonreturn-to-zero (NRZ) transceiver for low-power memory interfaces. The proposed transceiver (TRX) consists of a singleended transmitter (TX) and receiver (RX), achieving data rates of 15 Gb/s and 12 Gb/s, respectively, each incorporating a 2-tap feed-forward equalizer (FFE) and a 1-tap direct decision feedback equalizer (DFE). The quarter-rate clocking architecture, enhancing timing margin and power efficiency, is adopted in both the transmitter and the receiver. The TX utilizes a low voltage swing terminated logic (LVSTL) driver operating at a 0.5-V VDDQ and employs a 2-tap de-emphasis FFE to compensate for channel loss. The RX incorporates a 3-stage sampler structure. The 1-tap direct DFE effectively compensates for inter-symbol interference (ISI) caused by channel loss, improving signal integrity. Fabricated in a 28-nm CMOS process, the TRX achieves an energy efficiency of 0.64 pJ/bit at 15 Gb/s in the TX and 0.043 pJ/bit at 12 Gb/s in the RX, providing a solution for high-speed and low-power memory interfaces.

A Digitalized Chaotic Oscillator Probabilistic Bit for Static Annealing Ising Machine

2025-10-01T23:03:45+09:00

This work presents a digital tent-map chaotic oscillator (DCO)-based probabilistic bit (p-bit) architecture for compute-in-memory probabilistic computing applications. Unlike conventional p-bits, the DCO-based p-bit takes both advantage of high throughput and robustness of pseudorandom number generator (PRNG)-based p-bits and small area consumption of the analog domain p-bits. The DCO achieves high energy efficiency of 0.041 pJ/bit. We apply this noise generator to static annealing, a schedule that maintains fixed temperature during operation, and demonstrate its effectiveness on the Max-Cut problem. Compared to conventional thermal annealing approaches that rely on gradually changing temperatures, the static annealing scheme converges faster and achieves lower final Hamiltonian values in our experiments. Our findings highlight that static annealing is not only feasible but advantageous in solving complex problems with compute-in-memory hardware.

dVDS/dt Sensing Based Multi-Level Active Gate Driver IC for SiC MOSFETs

2025-10-01T23:04:42+09:00

Silicon carbide (SiC) MOSFETs are widely used in power electronics to achieve higher power density and efficiency. However, as switching speeds increase to enable high-density systems, issues such as voltage overshoot, false turn-on, electromagnetic interference (EMI) arise, degrading system performance and reliability. This paper proposes a multi-level active gate driver (AGD) IC based on Miller plateau detection to improve the switching characteristics of SiC MOSFETs. The switching performance of SiC MOSFETs using the proposed gate driver IC is validated through simulations in Cadence Virtuoso. During turn-on and turn-off events, the proposed AGD shows a 5% and 4% increase in ringing magnitude compared to a conventional gate driver IC, respectively, but improves the switching speed by 18% and 21%, demonstrating a better trade-off.

Temperature-Independent Current Reference with Tunable Temperature Coefficient DAC

2025-10-01T23:05:38+09:00

Modern automobiles increasingly support a variety of advanced features, with autonomous vehicle safety gaining heightened attention. This has created a growing demand for sensor technology that can accurately detect environmental changes. One of the critical challenges in automotive sensor technology is the need for a temperature-compensated reference. This paper focuses on designing a temperature-independent reference current source in this MPW. Conventional reference current sources are highly sensitive to environmental conditions, especially temperature fluctuations, leading to varying output values. Although several temperature-compensated reference current sources have been developed, effectively addressing the residual temperature coefficient resulting from process variations remains a challenge. To tackle this issue, we propose a circuit that compensates for residual temperature coefficients, enabling the creation of a stable, temperature-independent reference current source. This design aims to provide a reliable solution for the automotive sensor technology field, where maintaining accuracy across a range of environmental conditions is essential.

A 4x Time Interleaved SAR ADC with Common-Mode Injecting Skew-Detection Method

2025-10-01T23:06:25+09:00

This paper proposes a 4-channel time-interleaved successive approximation register analog to digital converter (TI-SAR ADC). The proposed TI-SAR ADC adopts a common-mode injection technique to achieve efficient skew detection. In addition, by employing a switched-capacitor integrator operating at a lower speed than the ADC sampling rate, low-power, background skew detection is realized. The proposed ADC achieves an SNDR of 61.3 dB at a sampling rate of 800 MS/s, while consuming 5.58mW of power and achieving a FoM_w of 7.73 fJ/conv-step.

A Temporal Interference Stimulation Driver IC with Unified Source and Sink Current Capability

2025-10-01T23:07:19+09:00

This paper presents a temporal interference stimulation driver IC (TIS-IC) for deep brain stimulation. The proposed MTIS-IC (Multi-TIS) features high linearity, independent frequency and amplitude control, and a highvoltage amplifier-based architecture. It achieves a peak-to-peak output voltage error within 0.4% and a maximum output current of 2 mA. Measured results show a maximum SFDR of 59 dB and a maximum SNDR of 46 dB. A proposed calibration method improves output signal accuracy and channel uniformity. Fabricated using a 180 nm BCD process, the proposed MTIS-IC overcomes the limitations of existing systems, enabling scalable neural stimulation and expanding biomedical applications

Design of an Energy-Efficient Neuron Circuit with Temporal Encoding for Capacitive Coupling Based Compute-In Memory Technology

2025-10-01T23:08:15+09:00

Matrix-vector multiplication (MVM) is a core operation in large language models (LLMs), and compute-inmemory (CIM) technologies offer a promising path to overcome data movement bottlenecks. Among them, capacitive coupling principle-based CIM (CCP-CIM) enables low-power operation by eliminating static current paths. In this work, we propose an energy-efficient neuron circuit optimized for CCPCIM. The design features a cascaded input stage for enhanced transconductance linearity, as well as feedback-assisted control and overflow/underflow detection to reduce unnecessary digital conversions. Furthermore, the discharge rate is dynamically adjustable through analog biasing, enabling flexible control of the neuron’s response range. Implemented in TSMC 28 nm CMOS, the proposed design achieves up to 2.15× less energy consumption than a conventional neuron circuit. This work supports scalable and adaptive analog inference for edge AI applications.

Implementation and Characterization of a Digital Phase-Locked Loop (DPLL) in 65-nm CMOS Technology

2025-10-01T23:09:03+09:00

This paper presents an experimental study on the influence of digital loop filter (DLF) gains K_P,PLL and K_I,PLL on the dynamic and noise performance of a 65 nm CMOS digital phase-locked loop (DPLL). By varying K_P,PLL and K_I,PLL across a range of values, the resulting changes in loop bandwidth, lock time, phase noise, and output jitter were measured. Silicon prototype measurements demonstrate that increasing K_P,PLL reduces lock time but may introduce peaking in the closed-loop response, whereas increasing K_I,PLL enhances low-frequency phase error suppression at the expense of slower settling. Under optimal gain settings, silicon measurements show an output spur level as low as −68.80 dBc and an RMS jitter of 0.638 ps, confirming excellent noise and spur performance.

Design of a High-Gain Low-Power K-Band Mixer in 65-nm Bulk CMOS Technology

2025-10-02T11:03:14+09:00

This paper presents a single-balanced down-conversion mixer for K-band applications requiring high conversion gain and compact integration. The proposed design incorporates gate inductive peaking at the RF transconductance stage to enhance the effective transconductance while simultaneously achieving input impedance matching. To address the limitations of conventional designs that require high LO drive levels, a transformer-based structure is introduced at the LO port, enabling differential LO injection and improved LO power efficiency. This configuration provides sufficient LO swing at the switching core without increasing power consumption or circuit complexity. The mixer is implemented in a 65-nm bulk CMOS process and occupies an area of 0.36 mm², including probing pads. Measurement results show impedance matching around 24 GHz for both LO and RF ports, along with an RF-to-LO isolation greater than 22 dB. The simulated conversion gain is 5.1 dB with a 5 dBm LO drive, an input 1-dB compression point of –18 dBm, and a noise figure of 15 dB at 24 GHz.

Analysis of Offset-Canceled DRAM Sense Amplifier

2025-10-01T23:10:53+09:00

This paper analyzes a DRAM sense amplifier (SA) architecture employing an offset cancellation technique using parasitic bit-line capacitance. The offset is stored through a diode-connected configuration without requiring additional calibration circuits, enabling a compact design. A prototype was fabricated in a TSMC 65 nm CMOS process and operated at 400 MHz. A built-in self-test (BIST) evaluates sensing accuracy by performing repeated write-and-read operations across 64 SAs. Measurements show that the standard deviation of input-referred offset decreases with longer offset cancellation (OC) time and saturates near 5 ns, indicating an optimal tradeoff between performance and power. The main sensing (MS) duration has minimal effect on offset characteristics, confirming that a 5 ns MS period ensures reliable operation. The architecture achieves effective offset cancellation with minimal overhead, making it well suited for scaled DRAM applications.

A Temperature-Compensated LDO without External Reference for Compact SoC Design in 65nm CMOS

2025-10-01T23:11:57+09:00

This paper presents a low-dropout (LDO) regulator with an embedded voltage reference (EVR), designed for system-on-chip (SoC) architectures requiring highperformance operation. The proposed design integrates the
voltage reference directly into the error amplifier (EA), enabling the generation of a 0.95 V output from a 1.05 V input while maintaining a low temperature coefficient and robust loop stability. The circuit comprises a proportional-to-absolutetemperature (PTAT) current generator, an EVR-based EA, and a power MOSFET. The LDO has been implemented in 65nm CMOS process. The simulation results demonstrate a stable output voltage of 0.95 V with a TC of 218 ppm/°C over a wide temperature range from -60°C to 120°C. A peak current efficiency of 99.99 % is obtained, maintaining stable operation and current driving capability up to 220 mA.