Journal of Integrated Circuits and Systems

On-Die Noise Monitoring Circuit for System-Level ESD

2024-09-30T15:30:19+09:00

Electrostatic discharge (ESD) poses a significant risk to electronic systems, potentially leading to operational malfunctions. Accurately assessing the noise waveforms induced within these systems is challenging due to various factors such as common mode (CM) noise, direct radiation coupling, and limited accessibility of external equipment. To tackle these hurdles, a novel approach involving an on-die monitoring circuit (OMC) has been proposed for integration within electronic systems. This embedded circuit enables precise measurement of noise without external interference. The OMC, can detect abnormal noise levels surpassing predefined thresholds on both signal and power networks, accurately capturing their waveforms. To validate its practicality, the OMC was implemented in a evaluation board and tested in ESD experiments. Unlike traditional oscilloscope equipment vulnerable to CM noise, the OMC successfully isolated and measured only the relevant differential mode (DM) noise generated within the system. This showcases its ability to isolate and quantify target DM noise even in complex environments, overcoming limitations of conventional equipment.

Floating Gate Radiation Sensor Interface ICs with Regulated-Cascode Current Reference and Time-Based Quantizer

2024-09-30T15:30:50+09:00

This paper proposes power-efficient ICs for measuring the signal of a Floating Gate (FG) radiation sensor. It implements the function of converting the current signal generated in the FG into a digital signal through a regulated-cascode current reference (RCCS) and a time-based quantizer. The proposed sensor interface ICs are implemented with the PDK of DB Hitek process, securing a 45 dB SNR with only 14.7 uW power consumption.

Frequency Reconfigurable Dual-Band Reflection-Type Phase Shifter with 360˚ Phase Shift Range for 5G NR FR2 Applications

2024-09-30T15:31:18+09:00

This paper proposes a frequency reconfigurable dual-band passive 360° reflection-type phase shifter (RTPS) for fifth-generation (5G) applications. The proposed phase shifter provides a full 360° phase shift range in multiple 5G new radio (NR) communication bands—n261 (27.5–28.35 GHz) and n260 (37–40 GHz)—using a transformer-based switchable inductor. The proposed transformer-based switchable inductor allows the operating frequency bands to be changed for achieving maximum phase shift range. Consequently, the proposed RPTS achieves a full 360° phase shift range with average insertion losses of 7.65 ± 2.08 and 7.03 ± 0.15 dB at 28 and 39 GHz, respectively. To the best of our knowledge, the proposed RTPS is the first dual-band RTPS to achieve a 360° phase shift in 5G NR FR2 applications.

Design of a Prototype 64−Channel ROIC for SWIR Imaging Sensor Applications

2024-09-30T15:31:46+09:00

This paper presents the design and validation of a 64-channel prototype Readout Integrated Circuit (ROIC) for InGaAs-based compound semiconductor pixels, specifically aimed at Short-Wave Infrared (SWIR) imaging systems. The ROIC, fabricated using a 0.18μm CMOS process, features an array of channels with a pitch of 50μm and a total chip area of 5 × 2.5 mm². Comprehensive silicon-level validation has been performed to ensure stability and performance reliability. The ROIC exhibits a random noise level of 116.28 μV_rms and operates with a total power consumption of 22.55 mW, demonstrating its suitability for infrared imaging applications. The study highlights the innovative approach of incorporating variable conversion gain and sensitivity adjustment to accommodate different pixel signal characteristics, thereby enhancing the overall imaging performance.

A Low-Power, Highly Linear Sub-GHz Receiver Front-End with a Voltage Follower-Based 4th-Order Channel Selection Filter

2024-09-30T15:39:24+09:00

A low-power highly linear sub-GHz receiver front-end employing a voltage follower based 4^th-order channel selection filter is proposed for low-power wide-area network (LPWAN) IoT applications. It consists of wideband single-to-differential (S-to-D) low noise amplifier (LNA), in-phase/quadrature (I/Q) passive mixer, and voltage-follower based 4^th-order channel selection filter. The proposed S-to-D LNA is designed on the basis of two cascaded inverters for S-to-D conversion and the correction amplifier to compensate the amplitude and phase imbalance and implement feedback. It shows relatively high gain, low noise, high linearity with simple hardware configuration and low power consumption The proposed channel selection filter is implemented using the more advanced source follower combining the flipped voltage follower (FVF) and super source follower (SSF), and the low power technique for implementing high-order filter is newly proposed in the design of channel selection filter. Eventually, the 4^th-order filter topology is devised without noise figure (NF) degradation compared to the 2^nd-order filter. In the simulation, the proposed receiver designed with a 130-nm CMOS technology shows the conversion gain of about 30 dB and double-sideband NF (NF_DSB) of 3.2 dB at 500 MHz operating frequency. The simulated output-referred third-order intercept point (OIP3) of the designed receiver ranges from +5 dBm to +7 dBm in sub-GHz band. The total power consumption of the receiver is 9.6 mW from a 1.2 V supply voltage.

Design of NRZ/PAM-3/PAM-4 Tri-Mode Single-Ended Transmitter for Next-Generation Memory Interfaces

2024-09-30T15:33:03+09:00

This paper presents a single-ended voltage-mode transmitter for next-generation memory interfaces, supporting three signaling modes: non-return-to-zero (NRZ), three-level pulse amplitude modulation (PAM-3), and four-level pulse amplitude modulation (PAM-4). Utilizing the same output driver, the tri-mode transmitter effectively reduces the development cycle and associated costs for IP development. Firstly, depending on the mode selection signal, two mode selectors determine which data are passed to the tri-mode driver, outputting the data in NRZ, PAM-3, or PAM-4 signaling. Secondly, 2-tap feed-forward equalizers (FFE) are separately applied to three modes, compensating for signal distortions caused by losses in signal transmission through the channel based on different FFE encodings. A seven-step four-point ZQ calibration is implemented to improve the level separation mismatch ratio. Designed using a 65-nm CMOS technology, the transmitter achieved data rates of 16-Gb/s in NRZ mode, 24-Gb/s in PAM-3 mode, and 32-Gb/s in PAM-4 mode.

A Photodiode Sensor Readout Circuit Utilizing a Differential Current Mirror for Dark Current Cancellation

2024-09-30T15:33:19+09:00

This paper proposes a differential current mirror circuit with built-in dark current cancellation for photodiode applications. The photodiode sensor, modeled with a diode and a parasitic capacitor, generates a current signal that is directed through two current mirrors. The signals from each current mirror are then differentially outputted. Thanks to the proposed differential current mirrors, the only high frequency signal current can be transferred to output port effectively. The proposed sensor interface ICs were implemented using the PDK of the DB Hitek process and achieved a dark current cancellation ratio of 40 dB at reconfigurable frequency.

A Cell-Based Implementation of ARM Cortex-M0 SoC

2024-09-30T15:38:23+09:00

For academic research purposes, ARM provided its SoC platform. This study presents the methods and results of implementing the Cortex-M0 as a chip. The behavioral memory was replaced with the foundry's memory, and the design was modified to allow software to be written externally to the chip at any time. During chip implementation, IDEC's guidelines were followed, utilizing as many tools as possible to increase the chip's functionality. The fabricated Cortex-M0 chip was mounted on a test board and was verified to work well in conjunction with the software. A hierarchical approach was adopted during the chip's implementation, with efforts made to minimize its size and facilitate its use as a platform. In this study, Samsung 28nm LPP process was applied