Journal of Integrated Circuits and Systems

Comparison of 3T2C Embedded DRAM in 28nm FD-SOI and Low Power Plus for Energy-Efficient Computing in Memory Architecture

2026-04-01T15:41:04+09:00

This paper presents a comparative analysis of a 3T 2C Embedded DRAM (eDRAM) bitcell fabricated in 28-nm LPP and FD-SOI processes for energy-efficient Computing-in-Memory (CIM) applications. eDRAM provides dense charge domain storage that is directly exploited for compact analog Multiply-And-Computation (MAC) operation in CIM arrays. The proposed cell employs a metal-oxide-metal (MOM) capacitor to achieve high capacitance density without additional process steps. Post-layout simulations and Monte Carlo analyses were conducted to evaluate the effects of the process and temperature variations and capacitive coupling on data retention and analog compute accuracy. Results show that the FD-SOI process provides enhanced retention characteristics and larger voltage margins owing to stronger capacitive coupling and reduced substrate leakage enabled by the buried oxide (BOX) layer.

Fast-Response Low-Voltage NMOS Low-Dropout Regulator Using Coarse and Fine Charge Pumps with Double Driving and High-Frequency Internal Oscillator

2026-04-01T15:41:55+09:00

A fast-response low-voltage NMOS low-dropout regulator (LDO) with coarse-fine charge-pumps and double driving-high frequency internal oscillator is proposed. It regulates the gate voltage of the power transistor through coarse and fine charge-pumps with three comparators for detecting coarse-fine modes. It achieves fast response time and low quiescent power loss. It has a low undershoot voltage with fast settling time employing a high-speed internal ring oscillator driving the coarse and fine charge-pumps. The LDO circuit is implemented with a 65 nm CMOS process. It generates 0.45 V output voltage from 0.5 V supply voltage. It has the simulation results of an overshoot of 34 mV, an undershoot of 69 mV, and a settling time of 28 ns under the load transient from 15 mA to 45 mA with a 1 ns edge.

Design of a High-Gain Amplifier Using Negative-Resistance-Assisted Technique

2026-04-01T15:42:19+09:00

This paper proposes an impedance‑splitting, negative‑resistance‑assisted architecture to improve feedback amplifier performance by implementing a negative resistance at the feedback nodes. This technique cancels non-ideal virtual ground (△V_VGND), thereby increasing the effective loop gain. Simulations show a low‑frequency gain increase of 43.6 dB and at least 39.8 dB improvements in both power-supply rejection ratio (PSRR) and common-mode rejection ratio (CMRR).

A 20-Gb/s/pin Single-Ended Transmitter with Capacitive Peaking Driver Based Crosstalk and Inter-Symbol Interference Compensation

2026-04-01T15:42:44+09:00

This paper presents a 20-Gb/s/pin single-ended transmitter that employs a capacitive peaking driver (CPD)- based crosstalk and inter-symbol interference (ISI) compensation technique, implemented in a 65-nm CMOS process. The CPD enhances high-frequency signal components and plays a central role in suppressing crosstalk and ISI, while its programmable capacitor bank enables adaptation to a wide range of channel-loss conditions. By generating the crosstalk compensation signal in advance from low-rate data of adjacent lanes, the proposed architecture achieves zero latency and aligns the shaping action with the expected disturbance window while incurring minimal power overhead, eliminating the need for highest-rate replica paths. Digitally controlled delay lines (DCDLs) further refine the timing of both crosstalk and ISI compensation. Post-layout simulation results demonstrate a horizontal eye-opening of 31.22 ps and a vertical eye-opening of 18.14 mV under a worst-case channel condition exhibiting 25.89 dB insertion loss at the Nyquist frequency. These results confirm that the CPD-based compensation scheme effectively mitigates crosstalk and ISI while maintaining energy-efficient high-speed signaling, making it a promising solution for future low-power, high-bandwidth serial interfaces.

7.5-GHz Low Local Oscillator Pumping Cryo-CMOS Parametric Amplifier for Quantum Computing

2026-04-01T15:43:09+09:00

This paper presents the design of a cryo-CMOS parametric amplifier suitable for operation at 4K and mK temperatures within the readout chain of quantum computers. It was experimentally verified that thermal noise introduced through the LO input path degrades the noise performance of the circuit. A parametric amplifier design capable of functioning with low local oscillator (LO) pumping power was proposed to mitigate this problem, providing a significant attenuation margin to safeguard against external noise. By optimizing the core parasitic resistance and adjusting the matching point, the parametric amplifier was measured 0 dB gain with 20 dBm LO power at 300K, and 15.2 dB gain with 0dBm LO power at 4K.

Design of Adaptive On-Time GaN DC-DC Converter with Active Gate Driving for Automotive System

2026-04-01T15:43:39+09:00

The proposed paper introduces a single-stage Gallium Nitride (GaN) DC-DC converter employing adaptive on-time (AOT) hysteresis control including an active gate driving bootstrap (BST) gate driver. To achieve optimal one-cycle transient response during load variations, it incorporates a sample and hold-based load detecting transient enhancer for precise detection of load changes and accurate control of on-time extension. Additionally, an active gate driver utilizing a dv/dt detector is designed and applied to independently control dv/dt and di/dt, mitigating the trade-off between electromagnetic interference (EMI) and switching loss. The converter was fabricated using a 0.18-µm HV BCD 1P6M process with a total chip area of 1.05 × 0.80 mm. It converts up to 60-V input down to 3-V and operates in the frequency range of 0.95–9.5 MHz. Designed to support a wide automotive battery voltage range from 7 to 60 V, post-layout simulations show the output voltage ripple is as low as 2.9 mV at 12 to 3 V conversion and 4.2 MHz switching frequency, achieving a maximum efficiency of 91.3%.

Design of a 2nd-Order Noise-Shaping SAR ADC Using Cascaded Floating Inverter Amplifiers

2026-04-01T15:44:08+09:00

This paper presents a 2nd-order noise-shaping successive approximation register (NS-SAR) ADC employing cascaded floating inverter amplifier (FIA) integrators. Key design considerations for the cascaded FIA-based loop filter are systematically analyzed and incorporated into the proposed architecture. The ADC is designed to achieve stable loop dynamics and enhanced noise-shaping efficiency while maintaining low power consumption. The chip was designed in a TSMC 0.18 μm standard CMOS process and achieves 83.98 dB SNDR, 89.15 dB SFDR, and a dynamic range of 83.04 dB while consuming 81.13 μW at a 2-MHz sampling rate with an oversampling ratio of 256, corresponding to a Schreier figure-of-merit of 160.80 dB.

Low-Complexity Referenceless Clock and Data Recovery with a Novel Alexander Phase-Frequency Detector

2026-04-01T15:44:41+09:00

This paper proposes a low-complexity referenceless clock and data recovery (CDR) circuit for high-speed serial communication systems. Its core contribution is a novel Alexander phase-frequency detector (APFD) that achieves a wide frequency acquisition range with minimal hardware overhead. The proposed APFD generates its frequency tracking signals by utilizing a single inverter on the conventional Alexander phase detector’s (APD) UP signal, eliminating the need for complex pattern decoding logic. We theoretically analyze the operational principle by modeling the probabilistic behavior of the detector's outputs, and our analysis is successfully verified through simulations, which show excellent correlation with the derived mathematical model. This APFD is integrated into a comprehensive 32 Gb/s quarter-rate CDR architecture. To ensure robust performance, the system incorporates an adaptive loop gain controller based on the signsign LMS algorithm and a direct proportional path with a deadzone mitigation technique to enhance high-frequency jitter tracking. By drastically simplifying the frequency detection mechanism, this work presents a promising solution for nextgeneration wireline transceivers that offers significant advantages in terms of circuit area and power efficiency.

Dynamic Multiplexer-Driven Level Shifter with High Common-Mode Transient Immunity and Sub-ns Transfer Delay for GaN Gate Drivers

2026-04-01T15:45:05+09:00

High-speed GaN gate drivers in half-bridge setups generate extreme voltage slew rates at the floating high-side node, compromising traditional level shifter reliability. Pulse-triggered designs face fundamental trade-offs between transfer delay reduction and common-mode transient immunity (CMTI) enhancement. This paper proposes a dynamic MUX-driven level shifter that senses internal latch nodes and high-side switch status to adaptively reconfigure current paths. During signal propagation, it enhances latch drive for accelerated transfer; during high-CMTI noise intervals, it maintains differential current balance to reject disturbances. Fabricated in 180 nm BCD process, the circuit achieves 886 ps delay and 200 V/ns CMTI, outperforming traditional PTAC designs for GaN applications.

A 100-MHz Multi-Step Pulse-Width Modulator for Low-Power Signal Isolation in Gate Drivers for Wide-Bandgap Devices

2026-04-01T15:45:26+09:00

High-performance and high-reliability gate drivers are essential for fully exploiting the switching capability of wide-bandgap (WBG) power devices. Due to the large voltage differences inherent to high-voltage power stages, robust signal isolation is required to reliably transfer control commands across domains. Inductive or capacitive coupling techniques are typically employed to achieve low-latency isolation, among which inductive coupling offers improved immunity to common-mode transient noise compared with capacitive counterparts. However, when the transmitted pulse width becomes excessively long, conventional inductive-coupling isolators suffer from substantial static current consumption, leading to increased power dissipation and thermal stress. To address these challenges, this work introduces a multi-step pulse-width modulator optimized for low-power isolators. Implemented in a 0.18-µm CMOS process, the proposed scheme conveys data through a short sequence of narrow, adjustable pulses rather than continuous current flow, enabling event-driven operation that substantially reduces average DC current. Post-layout simulations using a highly realistic transformer model with a 105 nH primary inductance and parasitic elements show that the isolator current can be tuned from 5.563 mA to 11.48 mA, significantly lower than the 20.86 mA required by the conventional approach. By lowering power consumption while preserving robust signal transfer, the proposed method supports higher system integration and improved long-term reliability.