Journal of Integrated Circuits and Systems

A High-Resolution Linear-Exponential Incremental Analog-to-Digital Converter With Digital Weight Compensation

2025-07-02T08:43:46+09:00

High-resolution analog-to-digital converters (ADCs) are essential for precise signal acquisition in applications such as medical imaging and high-quality audio systems. This paper presents a linear-exponential incremental ADC that addresses the key challenge of finite amplifier gain through a digital filter. Fabricated in a 65-nm CMOS process, the ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 87.3 dB and a total harmonic distortion (THD) of -101.8 dB for a 5.66 kHz input signal within an 18.75 kHz bandwidth. By compensating for analog imperfections in the digital domain, the proposed design achieves improved linearity and reliable high-resolution performance in demanding scenarios.

Impedance Measurement Integrated Circuit for Wireless Sensor Readout

2025-07-02T08:45:33+09:00

This chip detects the resonant frequency of an inductor-capacitor (LC) wireless sensor by analyzing its impedance characteristics. When wireless coupling occurs between the transmitter (TX) resonator and the receiver (RX) sensor, the impedance of the TX coil varies with the RX sensor’s frequency response. By analyzing the voltage variation across the TX resonator, the TX coil’s impedance can be determined, achieving resonant frequency detection of the RX sensor. Existing portable sensor readout systems using commercial ICs suffer from high complexity and power consumption. To address these issues, an impedance measurement IC is designed. The proposed IC extracts voltage characteristics at both ends of the TX resonator using a single-to-differential converter, mixer, level shifter, and low-pass filter. Therefore, the impedance of the TX coil is derived by dividing the two output DC voltages. Post-layout simulations with varying the TX coil resistance confirm that the measured values match the initial set values. The IC is designed using the TSMC 180nm RF CMOS process.

A CMOS-Based Ultra-Wide Range Temperature Sensor for Quantum Computing Circuits in 65nm CMOS

2025-07-02T08:46:18+09:00

In this paper, an ultra-wide range CMOS temperature sensor is designed for applications in cryogenic and room temperature environments. A beta multiplier structure is employed as the sensing element to generate a temperature-proportional current. By leveraging the temperature coefficient (TC) of MOSFET mobility and resistor characteristics, the sensor ensures a stable TC. The generated current serves as the bias for a relaxation oscillator, which facilitates temperature-to-frequency conversion. The relaxation oscillator operates with a lower TC than the beta multiplier, with its frequency variation determined by the bias current. The resulting frequency is then digitized using a 16-bit counter. The sensor is designed to operate over a temperature range of -270°C to 30°C. Simulation results indicate that the oscillator produces 20.6 KHz at -250°C with a TC of 0.75 KHz/°C.

Development of an Optimized Single-Slope Analog-to-Digital Converter Readout Circuit for Gas Sensing Systems

2025-07-02T08:47:24+09:00

This paper presents the design and implementation of a readout integrated circuit (ROIC) optimized for gas sensor applications. The proposed ROIC integrates essential components, including a ramp generator, digital DDR counter, comparator, and peripheral bias generation blocks, to ensure accurate signal processing. The ROIC achieves a power consumption of 1.31 mW and operates with a 1.2V input range, achieving a 62.5 kHz conversion rate and a performance of 9.41 bits effective number of bits (ENOB). Additionally, the figure of merit (FoM) of the system is measured at 30.81 pJ/step. The results indicate that the proposed ROIC provides a robust solution for high-precision gas sensing systems, demonstrating its potential to significantly enhance the performance of sensor-based applications, particularly in environments that require fast and accurate measurements. The chip, fabricated using TSMC 180nm CMOS technology, shows promise for real-world applications in industrial and environmental monitoring.

Design of a Spiking Neural Network Based on Stochastic Neuron

2025-07-02T08:49:16+09:00

In this study, we propose a 9×10 neuromorphic architecture that utilizes stochastic spiking neurons and SRAM as synapses. The stochastic spiking neuron features a capacitor-less structure, reducing hardware complexity and enabling low-power operation. Additionally, binary SRAM is employed as synapses to further enhance low-power characteristics. The proposed architecture was fabricated using the TSMC 28nm CMOS process. Simulation results confirm that the proposed design achieves a high energy efficiency of 60.55 TOPS/W. Through this approach, we aim to develop a low-power artificial neural network suitable for edge devices.

Latch Voltage Modulation of Cryptographic Transistor for True Random Number Generator

2025-07-02T08:50:01+09:00

We propose a latch voltage modulation of a single MOSFET functioning as a single-transistor oscillator with an analog-to-digital converter (ADC) for a true random number generator (TRNG). The MOSFET generates irregularly oscillating analog signals due to a single transistor latch with latch-up voltage (V_LU) and latch-down voltage (V_LD), which are then converted into digitized random numbers by the ADC. To achieve a controllable TRNG, it is crucial to examine how process parameters, such as the doping concentration of the p-well (N_pwell), the depth of the p-well (T_pwell), and the junction depth of the source/drain (x_j), influence V_LU and V_LD in a single-transistor oscillator implemented on a bulk-silicon wafer (1T-O_bulk). The randomly fluctuating output voltage (V_out), associated with V_LU and V_LD, serves as an entropy source for the TRNG. The random oscillation of V_out, generated at the drain of the 1T-O_bulk, was observed in a fabricated device using the TSMC 180 nm foundry process. Since aligning V_outfrom a 1T-O_bulk with the input voltage range of an analog-to-digital converter (ADC) is crucial, the three aforementioned major process parameters are tuned to control V_out. This approach contributes to advancing next-generation security technology.

A 5-GHz Multi-Modulus Divider with Duty Cycle Extension Re-Timer on 65-nm CMOS Technology

2025-07-02T08:50:57+09:00

In this paper, a multi-modulus divider (MMD) operating at 5 GHz has been designed using a 65-nm CMOS process. The MMD core is composed of cascaded DIV2/3 cells. The first three stages were composed of TSPC D-flipflop, and the last stage was composed of static D-flipflop. We propose a re-timer that extends the duty cycle by generating an asynchronous reset through digital logic gates. This not only removes accumulated circuit noise, but also generates a duty cycle from at least 43% to 53% depending on the division ratio. Based on the output frequency of 200MHz, when N is 25, the total power consumption is 0.9mW, and the circuit size is 75μm*30.5μm.

Isolated Multi-Cell Single-Path Battery Management System for Electric Vehicle Batteries

2025-07-02T10:21:03+09:00

A Battery Management System (BMS) is essential for monitoring battery voltage and maintaining balance in high-voltage environments. This study applies an indirect measurement approach using an isolated structure, where LEDs are used for voltage sensing and balancing. In order to monitor the accurate voltage even in the PVT environment, the multiple battery voltages were monitored with a multi-cell single path structure, and an internal reference voltage was generated to ensure the monitoring result compensated for temperature, even with battery temperature changes. BMS executes to get cell monitoring and reference voltages in one output port while performing temperature compensation, andindependently, the cell-by-cell register operation method allows simultaneous balancing of multiple cells. As a result of the design, the voltage resolution within +/-5mV from -20 degrees to +80 degrees was secured, and the balancing operation was secured at more than 20mA. This allows the battery voltage monitoring and cell balancing to be stable with the proposed isolated circuit structure in high-voltage environments.

Four-Phase Always Quadra-Path Hybrid DC-DC Converter with Output Capacitor Free

2025-07-02T08:51:59+09:00

This paper presents a four-phase always quadra-path (AQP) DC–DC converter designed to achieve high power density and power conversion efficiency with low output ripple. The proposed architecture consists of one inductor path and three capacitor paths operating in a time-interleaved manner to collectively deliver the output current. This structure reduces the inductor’s DC current stress, enabling the use of a compact inductor without sacrificing efficiency or transient performance. The converter supports an output voltage range of 0.3–2.0 V from a 5 V input supply, making it suitable for battery-powered and low-voltage SoC applications. The hybrid current delivery through capacitive and inductive paths improves transient response and ripple suppression. Measurement results show a peak power conversion efficiency (PCE) of 74% and a maximum load current of 2 A. The converter is implemented in a TSMC 180 nm BCD process, occupying a 3 mm × 3 mm (9 mm²) silicon area.

Power and Data Transmission for Wireless Electroceutical System

2025-07-02T08:52:26+09:00

TThis paper reviews the design concepts and constraints of current wireless power and data transmission technologies (e.g., inductive coupling, optical transmission, and ultrasonic-based techniques), and concentrates on the design and implementation of the proposed inductive coupling method for electroceutical applications. Especially considering miniaturisation and biocompatibility, our approach has the potential to become a competitive therapeutic alternative in many clinical settings in the future, since it guarantees more stable data communication and higher power transfer efficiency than current techniques. The chip is fabricated using the TSMC 180 nm CMOS process, and the size is 1 mm x 1 mm.