Journal of Integrated Circuits and Systems

Wordline Driver for Processing-in-Memory Using the Input Bit-Slicing Method

2026-07-01T09:03:15+09:00

The von Neumann bottleneck, caused by the performance gap between memory and processing units, has become a critical issue in modern computing systems. This bottleneck fundamentally limits system throughput and energy efficiency. It becomes particularly critical as data-centric applications continue to demand higher bandwidth and faster access. To overcome this limitation, analog processing-in memory has emerged as a promising candidate to address this challenge. In this work, we designed a wordline driver for processing-in-memory systems that use the input bit-slicing method, where fixed-length binary pulses serve as inputs. The proposed wordline driver was fabricated using the TSMC 180 nm CMOS logic process. Measurement results confirm that the wordline driver successfully generates 4-bit fixed-length binary pulses at the desired voltage levels, ensuring reliable wordline activation during input bit slicing. To provide a system-level context, we also describe a successive integration-and-rescaling neuron fabricated on the same 180 nm CMOS wafer. The integration of the proposed driver with this neuron was established in our prior work, reinforcing the claim that it effectively supports robust input bit-slicing operations in processing-in-memory architectures. Ultimately, these results confirm the feasibility of the proposed wordline driver for use in practical analog processing-in-memory systems.

A High-Voltage DC-DC Buck Converter with Dual-Parameter Maximum Power Point Tracking for Triboelectric Nanogenerator Energy Harvesting

2026-07-01T09:03:24+09:00

This work presents a high-voltage (HV) energyharvester interface integrated circuit (EHI-IC) designed for efficient energy extraction from triboelectric nanogenerators (TENGs) operating in high-impedance, low-frequency oceanic environments. TENGs produce short-duration, HV pulses with equivalent source resistances in the 2–10 MΩ range, posing challenges for conventional power management circuits. The proposed EHI-IC incorporates a full-bridge rectifier followed by an HV DC-DC buck converter with a dual-parameter maximum power point tracking (MPPT). A voltage-to-current calibration block and a power-to-bit converter provide digital monitoring of input power, enabling dynamic adjustment of the converter duty cycle to maximize power transfer. Zero-currentswitching (ZCS) control ensures precise timing of power switches, minimizing reverse current and improving efficiency. Fabricated in a 0.18-μm HV bipolar CMOS-DMOS (BCD) process with a compact 3 mm² footprint, the EHI-IC achieves output voltage between 1.3 and 1.8 V and MPPT efficiencies up to 95.5%. The end-to-end efficiency of EHI-IC achieved 90.4% with a power consumption of 926.8 nW. Experimental and simulation results validate reliable operation for self-powered Internet of Things (IoT) and wearable applications.

FPGA-Based Digital Controller for High-Speed CAN Flexible Data-Rate Communication

2026-07-01T09:03:33+09:00

This paper presents the design and implementation of an FPGA‑based CAN‑FD digital controller optimized for in‑vehicle communication. The proposed controller is organized into modular components, including a transmitter, receiver, error handler, CRC unit, and bus monitor, to ensure accurate protocol handling and stable bit timing across both arbitration and data phases. A bus‑monitor‑centric synchronization method is introduced to enhance timing precision and improve robustness under high‑speed data‑rate switching. The controller was implemented on the AMD Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit and tested with an external CAN‑FD node with an MCP2562FD transceiver and an MCP2518FD-based CAN‑FD shield. Experimental results demonstrate successful transmission and reception of 64‑byte payloads at 4 Mbps without protocol violations, confirming that the proposed architecture is suitable for practical deployment in automotive and industrial applications.

Fill Factor Preservation in Front-Side Illuminated Single-Photon Avalanche Diode Arrays Using External Routing

2026-07-01T09:03:41+09:00

In recent years, Back-Side Illumination (BSI) has emerged as a prominent configuration for Single-Photon Avalanche Diode (SPAD) arrays, offering excellent photon detection probability (PDP). However, this comes at the cost of high fabrication complexity, reduced yield, and even degraded PDP at certain wavelengths. As a result, Front-Side Illumination (FSI), which implements the SPAD in a standard CMOS process, remains a practical and attractive alternative. In FSI-based SPAD systems, components such as quenching circuits, counters, and TDCs typically reduce the fill factor of individual pixels or the overall array. This work proposes a novel routing scheme that enables area-intensive digital components to be placed outside the array boundary. The proposed structure preserves the fill factor at both the pixel level (4.48%) and the array level (5.19%), compared to the intrinsic SPAD fill factor (5.84%), while successfully demonstrating full system functionality through pattern projection measurements.

A 2-Level Buck Converter Using Adaptive ON/OFF-Time Control for Frequency-Stable Operation

2026-07-01T09:03:48+09:00

This paper presents an adaptive ON/OFF-time (AOOT) control technique for a 2-level buck converter designed in a 180-nm BCD technology. Conventional adaptive on-time (AOT) control provides a simple comparator-based structure; however, its fixed on-time operation inherently results in switching-frequency variation and ripple-dependent behavior, which can lead to sub-harmonic oscillation under wide operating conditions. The proposed AOOT scheme adaptively generates both ON- and OFF-time according to the input and output conditions, thereby enabling direct regulation of the switching period and reducing ripple-dependent instability associated with conventional AOT control under the simulated operating conditions, without requiring a complex compensation network. A 1-MHz buck converter is evaluated in simulation with a 2.5-V input, supporting a wide output voltage range from 0.5 to 2.0 V and a maximum load current of 2.5 A (5-W output power). Simulation results demonstrate that the proposed AOOT control maintains a near-target 1-MHz switching period under the representative simulated load and output voltage conditions, while achieving predictable steady state operation. The proposed AOOT adaptively generates both ON- and OFF-time according to operating conditions, enabling direct regulation of the switching period while reducing the dependence on output-ripple-based retriggering without high order compensation or ripple-injection circuits.

Total-Ionizing Dose Effects in CMOS Operational Amplifiers with NMOS and PMOS Differential Pairs

2026-07-01T09:03:59+09:00

This paper investigates the impact of total ionizing dose (TID) effects on two-stage CMOS operational amplifiers employing NMOS and PMOS differential input pairs. Previously reported TID-induced threshold voltage shifts for a 180-nm CMOS process are adopted and applied at the circuit level through controlled gate voltage offsets for a fair comparison under identical design constraints. The transistor width and length are fixed, and the effective device size is adjusted by varying the number of transistor fingers to match bias conditions and power consumption between the two amplifier configurations. Circuit-level simulations are performed under a TID condition of 125 krad (SiO₂) and compared with pre-irradiation baseline results. The results show that both NMOS and PMOS differential pair amplifiers maintain stable operation without functional failure. Key small-signal performance metrics, including DC gain, bandwidth, and phase margin, exhibit only moderate changes while stable operation is preserved after TID exposure. In contrast, power consumption shows a more noticeable increase, particularly in the NMOS-input amplifier, reflecting a stronger sensitivity of bias current to TID-induced device degradation.

A Leakage-Attenuated Auto-Zeroing High-Pass Filter Using Switch Voltage Regulation

2026-07-01T09:04:08+09:00

This paper presents leakage-attenuated feedback (LAF) auto-zeroing high-pass filter (AZHPF) for various analog front-end applications. AZHPF is widely used to cancel DC offset. However, AZHPF suffers from leakage induced voltage decay during auto-zeroing phase. This leads to large offset error and performance degradation particularly at low operation frequency. To overcome this limitation, LAF is proposed. As a result, the proposed LAF AZHPF achieves improved offset cancellation. Simulation results verify the effectiveness of the proposed approach, making the proposed AZHPF suitable for low-frequency precision applications. In this proposed design, an error amplifier is used to regulate the voltage across the switches connected to the sampling capacitor. By maintaining equal voltage levels at both switch nodes, the stored offset voltage is preserved over time without increasing the sampling capacitance. Simulation results demonstrate the proposed design successfully achieves lower offset error than the conventional design over wide range from 10 mHz to 1 kHz. In particular, the proposed approach validates its effectiveness as a general solution for leakage current prevention at low frequency in auto-zeroing circuits.

A 1-Gb/s DDFS-based Baseband FDMA 8-Qubit Controller

2026-07-01T09:04:16+09:00

We propose a direct digital frequency synthesizer (DDFS) based baseband multi-qubit controller with integrated pulse shaping and digital-to-analog converter (DAC). It supports eight multi-qubit control and four pulse shapes operating at 1 GHz clock speed. The digital baseband waveform generator offers programmable frequency, phase, amplitude, and pulse envelope. Pulse shaping demonstrates significant sidelobe suppression, leading to reduced adjacent channel interference. Clock gating is applied, resulting in a 9.46 % reduction in power consumption for single qubit control. The proposed baseband controller is implemented in 65 nm low-power (LP) CMOS process and achieves 62.13 dB of spurious-free dynamic range (SFDR) at the single frequency output signal. The total active area of the chip is 4 mm2.

A 0.0031-mm2 6-Bit 400-MS/s Charge-Injection DAC Based Loop Unrolled Asynchronous Successive Approximation Register ADC

2026-07-01T09:04:27+09:00

This paper presents a 6-bit charge-injection DAC based loop unrolled SAR (ci-LU SAR) ADC targeting high speed and area-efficient column readout for highly parallel computing-in-memory (CIM) macros. To reduce the dominant DAC area overhead in prior LU SAR ADCs, the proposed architecture replaces the conventional CDAC with a charge injection DAC (ciDAC) while preserving the sequential domino-style comparator operation of LU SAR conversion. A self-calibrating offset-cancellation scheme is applied to each comparator to mitigate comparator offset mismatch, which is critical in multi-comparator LU architectures. Implemented in 65-nm CMOS, the ADC achieves 400 MS/s with a 1.0-V supply while occupying 0.003157 mm2 core area, where the DAC network accounts for only 11.3% of the core area. Post-layout simulations show 35.73-dB SNDR and 47.86-dB SFDR at Nyquist input, with 3.36-mW power consumption, 168 fJ/conversion-step Walden FoM, and 5.64-bit ENOB.

Hardware-Efficient Accelerator for Spiking Neural Networks with Synchronous Spike Storage and Weight Address Control

2026-07-01T09:04:38+09:00

Spiking neural networks (SNNs) are attracting attention for their energy-efficient computation and real-time processing capabilities, as they emulate the time-based signal processing of the human brain. However, prior hardware implementations have the disadvantages of high resource usage and long inference latency. To solve this problem, we present a hardware-efficient FPGA-based SNN architecture. Through voltage scaling, hardware-efficient optimization of synaptic transmission delay, and reformulation of the neuron equation with power-of-two scaling, hardware resources are greatly reduced. Furthermore, the synchronous spike storage and controller modules are introduced to simplify the data path. The proposed design was implemented on the XC7Z7020 board, achieving an inference latency of 1.41 ms/image and a 103.8× speedup over the CPU on the MNIST dataset with only a 0.3% accuracy drop.

An mm-Wave Wilkinson Combiner with Stacked Coupling and Capacitive Loading Technique

2026-07-01T09:04:45+09:00

This paper introduces a small Wilkinson power combiner (WPC) created in a 0.18 μm CMOS process for use in millimeter-wave systems. The suggested combiner substitutes typical λ/4 microstrip arms with stacked coupled transmission line segments, which are made on the uppermost metal pair (M5/M6). This allows for significant vertical coupling and field confinement, which raises the effective phase constant and decreases the physical arm length. Furthermore, distributed capacitive loading is added along the arms to create a slow wave effect and adjust the arm susceptance for better input matching. A small trim capacitor at the combining node also corrects for any remaining pad/transition reactance. Measurements taken around 60 GHz show an insertion loss of 0.6 dB, a return loss of -19 dB, and an isolation of -36 dB within a small area of 0.28 mm2. In comparison to current CMOS combiners, the presented method strikes a good balance between size reduction and electrical performance, delivering a CMOS-compatible, low loss, and high isolation option ideal for compact millimeter-wave phased-array and highly integrated front-end systems.

A 6-Bit 2GS/s Sampling-Rate 27.8fJ/Conversion-Step 610-μm2 Successive Approximation Register Time-to-Digital Converter

2026-07-01T09:04:53+09:00

This paper proposes a small-area, low-power, and high-speed 6-bit SAR time-to-digital converter (TDC) for time interleaved ADCs. The proposed architecture utilizes a selective delay tuning (SDT) cell to achieve a relatively large reference time step (TLSB) of 4 ps. A TLSB of 4 ps provides sufficient margin to ensure that the SAR TDC’s performance remains dominant over the jitter from voltage-to-time converter (VTC) and TDC delay line thereby preventing SNDR degradation. Fabricated in a 28nm CMOS process, the proposed TDC occupies an active area of only 610 um2. Proposed SAR TDC consumes 2.8mW from a 0.9V supply voltage. At a sampling rate of 2 GS/s, the design achieves an SNDR of approximately 36 dB. The proposed TDC demonstrates a compact area compared to prior arts and achieves a Nyquist FoMW of 27.8 fJ/conv-step.

A GaN Gate Driver with Integrated Protection Circuit

2026-07-01T09:04:59+09:00

This paper proposes a gate driver IC with integrated protection circuits to enhance reliability in high speed power conversion systems. Although GaN power devices are widely adopted to achieve high power density and high conversion efficiency, their relatively immature technology and limited robustness necessitate the use of dedicated protection circuits.

The proposed gate driver employs a separated output buffer structure to prevent short-circuit current during switching transitions and allows independent adjustment of turn-on and turn-off times through external gate resistors. In addition, a low-power hysteretic under voltage lock-out (UVLO) circuit is incorporated to ensure stable operation during power-up and power-down processes while minimizing static current consumption. To suppress false triggering caused by switching noise, a leading edge blanking technique is applied in the over current protection (OCP) scheme. Furthermore, a fault reset time–based protection mechanism is introduced to mitigate fault chattering resulting from repetitive over-current events.

A Highly Linear Modified Super Source Follower-Based Active Feedback Wideband LNA for Sub-GHz Wireless IoT Application

2026-07-01T09:05:36+09:00

This paper presents a highly linear modified super source follower (SSF)-based active feedback wideband low noise amplifier (LNA) for sub-GHz wireless Internet-of-Things (IoT) applications. To further increase the loop gain and improve both the noise figure (NF) and linearity of the LNA, it is necessary to reduce the output impedance of the voltage follower in the feedback path so that it behaves more like an ideal voltage buffer. To achieve this, the proposed wideband LNA employs an advanced source follower (modified SSF) by combining a flipped voltage follower (FVF) with an SSF, forming a voltage buffer within the feedback path. Two feedback paths are utilized to increase the loop gain and enhance the effective transconductance of the input transistor in the advanced SSF. Additionally, to further increase the loop gain, the LNA output signal is applied to the gate of transistor, which serves as the current source device in the modified SSF within the feedback path. This approach directly reduces the output impedance while improving loop gain, noise performance, and linearity. The proposed LNA was designed using a 130-nm CMOS technology. Experimental results show that the input return loss (S11) is less than −10 dB up to 2 GHz, the power gain (S21) is 21 dB, and the NF is 1.6 dB at 900 MHz. The measured 3-dB bandwidth exceeds 2 GHz, and the input third-order intercept point (IIP3) ranges from −6 dBm to −4 dBm with a two-tone spacing of 20 MHz. The total power consumption is approximately 12.5 mW from a 1.2 V supply.