Journal of Integrated Circuits and Systems

H-Band 4-Array Frequency-Locked Oscillator ICs Packaged in an Oversized Waveguide Channel

2025-04-01T14:33:30+09:00

This paper presents the design and analysis of a 4-array oscillator module based on InP 250 nm HBT technology, with a focus on spatial power combining. Four identical oscillator ICs were integrated into a 1720 µm extended waveguide, and individual biasing was applied to achieve frequency locking at 262.7 GHz. While locking was successful, power combining through the binary channel could not be achieved due to phase mismatches between oscillator elements. Radiation pattern measurements confirmed out-of-phase locking, and the Total Radiated Power (TRP) reached 6.1 dBm, representing a 6.1 dB increase over a single module. These results highlight both the potential and the challenges of spatial power combining for high-frequency oscillator arrays.

A Low-Power CMOS Optoelectronic Receiver Array for LiDAR Sensor Applications

2025-04-01T14:33:38+09:00

This paper presents a power-efficient receiver topology for short-range LiDAR sensor applications by utilizing a 180-nm CMOS technology. The proposed design includes a fully differential transimpedance amplifier (TIA) with on-chip avalanche photodiodes and a time-to-voltage (T2V) converter. Post-layout simulations reveal that the T2V converter handles the input photocurrents from 40 μA_pp to 5.8 mA_pp for the detection range as short as 30 centimeters. The single-channel LiDAR receiver consumes 10 mW from a single 1.8-V supply and covers a detection range of 0.3 to 22.8 meters. The whole 4x6 channel optoelectronic receiver array occupies an area of 1.5 x 2.0 mm², including I/O pads.

Input-Signal-Based Power-Gated Single-Slope ADC for Low-Power CMOS Image Sensors

2025-04-01T14:33:49+09:00

This paper presents a low-power single-slope analog-to-digital converter (SS-ADC) that uses two comparators of the same structure to predict when a comparator flips. One of the comparators, a replica comparator, uses only half the bias current compared to the main comparator, causing the output of the comparator to flip early. By predicting the flipping time of the comparator in advance, power-gating techniques can be applied, resulting in reduced dynamic power consumption. The proposed 11-bit SS-ADC is fabricated using a 28-nm standard process, considering a resolution of 320 × 240 and an operating frame rate of 133 frames per second. Measurement results demonstrate that the power consumption of the proposed SS-ADC has decreased by approximately 17.6%. The total power consumption per column is 4.8 μW, and the figure of merit is 76.4 fJ/conversion step.

Design of a Buck-Boost Converter without Output Capacitor for Driving Automotive LED

2025-04-01T14:34:01+09:00

LEDs are widely used in automotive lighting systems due to their long lifespan, low power consumption, and fast response characteristics. Consequently, significant research has been conducted on LED drivers. Automotive LED drivers must rapidly adjust their output voltage to accommodate the wide input voltage range of vehicle batteries (7-60V) and the operating conditions of LED matrices. While buck-boost converters are commonly used for this purpose, conventional converters face the risk of LED damage caused by input voltage fluctuations and LED switching, primarily due to the presence of an output capacitor. To overcome this limitation, this study designs of a buck-boost converter without an output capacitor. The designed buck-boost converter utilizes a flying capacitor structure, ensuring that LED current is always supplied through the inductor. Additionally, by adopting LED current-based feedback, both the current regulator and reference voltage controller are eliminated. The designed converter maintains a stable output voltage and LED current across an input voltage range of 7-60V. The chip was fabricated using TSMC’s 180nm BCD process.

An Adaptive Gate Driver-Assisted Continuously Scalable-Conversion-Ratio Switched-Capacitor Converter

2025-04-01T14:34:19+09:00

This paper presents an adaptive gate driver-assisted continuously scalable-conversion-ratio (CSCR) switched-capacitor (SC) DC-DC converter. Gate-source voltage controller (GSVC) generates dynamic supply voltage to the gate driver adaptively according to the output voltage level of the converter. By adopting an adaptive gate driver to achieve soft charging between capacitor connections, the overall system generates a wide range of output with high power density and power conversion efficiency. The proposed converter generates an output range from 0.7 V to 1.8 V from an input voltage of 2.9 V. The proposed converter achieves a peak PCE of 72%. The proposed converter is implemented in TSMC 180 nm BCD process, with a chip area of 3 mm x4 mm.

Capacitor-Free Event-Based Asynchronous Digital LDO Regulator with 99.99% Current Efficiency

2025-04-01T14:34:34+09:00

This paper proposes a high-performance digital low-dropout regulator (DLDO) for wearable devices and IoT applications. The proposed DLDO circuit design provides fast stability and low power consumption using a PID controller and event-driven digital feedback control. The circuit utilizes a high-speed Flash-SAR ADC to feedback on the output, enabling real-time adjustment of the PID controller parameters to quickly adapt to external environmental changes and achieve a fast settling time. The proposed event-driven method minimizes circuit operation to reduce power consumption. Additionally, the limit-cycle oscillation typically occurring in the steady state is suppressed, thereby reducing output voltage ripple.

The circuit is fabricated using a 55-nm CMOS process, with a chip area of 1800 x 1820 um². The proposed design supports an input voltage range of 0.5 – 1.2 V and an output voltage range of 0.4 – 1 V. It achieves a fast-settling time of 252 ns and a low current consumption of 1.7 µA at a 50MHz operating frequency. The peak current efficiency is 99.99%, with a maximum load current of 70 mA. The load regulation is 0.13 mV/mA, and the line regulation is 0.01 V/V.

A Resolution-Configurable Charge-Domain Capacitance-to-Digital Converter

2025-04-01T14:34:50+09:00

This paper presents a semi-digital capacitance-to-digital converter (CDC) with an extended input capacitance range of up to 1 nF, leveraging a configurable charge subtraction capacitor and a current mirror-based discharger to maintain high resolution. The proposed CDC employs a single-slope discharge mirror technique to achieve energy-efficient operation while eliminating complex analog circuits such as operational transconductance amplifiers (OTAs). The current mirror-based discharger with a charging flag mechanism enables precise charge sensing by dynamically controlling the charging and discharging processes, ensuring accurate capacitance. Additionally, this structure reduces circuit complexity while maintaining measurement accuracy and extending the supported input capacitance range. The configurable charge subtraction capacitor array further enhances flexibility, making the design suitable for various capacitive sensing applications, including pressure, humidity, and touch sensing. Post-layout simulations in a 180 nm CMOS process demonstrate a consistent conversion time across a wide capacitance range while maintaining low power consumption. Measurement results confirm a minimum resolution of 10 fF for a 1 nF input capacitance with single slope regulation.

EIT System with Skip Pattern Application: Enhanced Target Image Reconstruction Methodology

2025-04-01T14:35:05+09:00

This paper presents a method for implementing skip patterns in Electrical Impedance Tomography (EIT) systems, which improves upon the limitations of the conventional adjacent method in image reconstruction. By applying skip patterns, we achieve a more uniform current distribution, thereby enhancing the ability to reconstruct target images. This approach provides a flexible and efficient framework suitable for various EIT applications across multiple industries, including medical imaging and industrial process monitoring.

A Fast Adaptive and Fine Stabilizer Based Digital LDO

2025-04-01T14:35:15+09:00

In this brief, fully integrated digital low-dropout regulator (DLDO) is proposed to address the trade-offs between transient response and power efficiency in dynamic load conditions. The design features a fast-adaptive glitch-driven coarse loop controller, which rapidly adjusts PMOS switches using precisely generated pulses, minimizing transient recovery time (T_REC) even during large load current (I_LOAD) changes. Additionally, a fine voltage stabilizer ensures steady-state voltage stability by employing high-resolution PMOS control. The DLDO is fabricated in a 65-nm CMOS process, the proposed DLDO supports an input voltage range of 0.6 V to 1.2 V and achieves a regulated output voltage from 0.55 V to 1.15 V. Simulation results demonstrate a 264 mV voltage droop recovery within 19.11 ns for a 26 mA load step, achieving a figure-of-merit of 0.225 ns² and a peak current efficiency of 99.32%. The low quiescent current of 157 μA makes it highly suitable for power-efficient SoC applications requiring both fast transient response and precise voltage regulation.

Neural Recording with Auto Noise Calibration to Reduce Multichannel Variation

2025-04-01T16:11:15+09:00

Recording neural signals and transmitting measurement data wirelessly is crucial for implementing closed-loop neural stimulation systems. This work achieves a dynamic range of over 90 dB by employing delta-sigma and auto-ranging structures in an integrated circuit (IC) chip. Traditional wireless data transmission methods such as Bluetooth, inductive coil, and RF communication pose challenges including large spatial requirements, movement restrictions, and low data transmission rates relative to power consumption. To address these limitations, this research adopts optical communication techniques for wireless data transmission from freely moving multiple experimental animals. Additionally, noise calibration logic is designed to reduce channel mismatches. The IC chip, fabricated in a standard 65nm CMOS process, has a size of 1 mm² and consists of 8 channels.