1.
Han I-H, Choo M-S. Implementation and Characterization of a Digital Phase-Locked Loop (DPLL) in 65-nm CMOS Technology. JICAS [Internet]. 2025Oct.1 [cited 2025Oct.10];11(4):52-7. Available from: https://jicas.idec.or.kr/index.php/JICAS/article/view/318