1.
Lee J-C, Chae J-H. Design of 2.5-Gb/s Parallel PRBS Generator and 4-Gb/s Area Efficient PRBS Checker in 65-nm CMOS Process. JICAS [Internet]. 2024Jan.1 [cited 2024Nov.21];10(1). Available from: https://jicas.idec.or.kr/index.php/JICAS/article/view/226