KO, Jeong-Eun; CHOI, Woo-Vin; KIM, Min-Seok; CHAE, Joo-Hyung. Hardware-Efficient Accelerator for Spiking Neural Networks with Synchronous Spike Storage and Weight Address Control. Journal of Integrated Circuits and Systems, [S. l.], v. 12, n. 3, p. 57–62, 2026. DOI: 10.23075/jicas.2026.12.3.010. Disponível em: https://jicas.idec.or.kr/index.php/JICAS/article/view/382. Acesso em: 29 oct. 2026.