Han, I.-H. and Choo, M.-S. 2025. Implementation and Characterization of a Digital Phase-Locked Loop (DPLL) in 65-nm CMOS Technology. Journal of Integrated Circuits and Systems. 11, 4 (Oct. 2025), 52-57. DOI:https://doi.org/10.23075/jicas.2025.11.4.009.