Journal of Integrated Circuits and Systems

Design of 1:1 Transformer based 2-Stage Differential Low-noise Amplifier for W-band Radar

Jaeeun Lee, Choul-Young Kim — Mon, 01 Apr 2024 00:00:00 +0900

This paper introduces a 77-81 GHz CMOS low-noise amplifier (LNA) designed for FMCW radar applications, with the goal of achieving high gain and low noise figure. To attain these objectives, a two-stage differential common-source (CS) structure is adopted, and neutralization capacitors are employed in each stage to obtain high gain. The proposed LNA is implemented in bulk CMOS 65 nm process, providing a gain of over 17 dB and a noise figure of less than 4.5 dB in the frequency range of 77-81 GHz. The chip size, including pads, is 0.69 μm 0.39 μm.

Ka-band CMOS Power Amplifier with Self-Biasing-Resistor

Younseok Han, Gwanghyeon Jeong — Mon, 01 Apr 2024 00:00:00 +0900

In this paper, a CMOS power amplifier using a self-biasing-resistor transistor for Ka-band is proposed. Generally, when designing a power amplifier with a cascode structure, a structure connecting the source and body of the transistor is used. This changes the intercascode voltage depending on the output of the common source stage, which changes the body voltage of the common gate stage, ultimately changing the I-V curve. Therefore, by inserting a large resistor between the body and the source, parasitic capacitors are used to split the RF swing in the body and compensate for voltage changes. As a result, AM-AM and IMD3 have been improved, and it has a linear output power of 13.1dBm and a linear PAE of 22.6% at a supply voltage of 2.4V.

Design of a 128x128 ROIC Array for Development of Uncooled 2.6 μm-wavelength SWIR Imaging Camera

Min-Jun Park, Ji-Yeon Jeon, Sang-Jun Lee, Hyeon-June Kim — Mon, 01 Apr 2024 00:00:00 +0900

This paper details the development and extensive silicon-level verification of a 128 × 128 readout integrated circuit (ROIC) tailored for uncooled short-wave infrared (SWIR) imaging cameras, which operate at a 2.6 μm wavelength. We conducted silicon-level verification of the developed ROIC, enabling a detailed analysis of various performance aspects. This evaluation will help us identify potential explore for further improvements, significantly advancing SWIR imaging camera systems. Our goal is to gain a deeper understanding of performance dynamics to enhance operational efficiency and image quality. The prototype ROIC was manufactured using a 0.18-μm 1P6M CMOS process, featuring an effective pixel resolution of 128 (H) × 128 (V), specifically designed for InGaAs FPAs. The prototype consumes 42.25 mW of power and achieves a frame rate of 390 frames per second.

A Current-Mode VCSEL Driver for Short-Range LiDAR Sensors in 180-nm CMOS

Xinyue Zhang, Yeojin Chon, Shinhae Choi, Sung Min Park — Mon, 01 Apr 2024 00:00:00 +0900

This paper presents a current-mode VCSEL driver (CMVD) implemented in a 0.18-m CMOS technology for the applications of short-range LiDAR sensors, where a current-steering logic is exploited to deliver simultaneously the modulation currents (from 0.1 to 10 mA_pp) and the bias current of 0.1 mA directly to the VCSEL diode. For simulations, the VCSEL diode is modeled as a 1.6-V forward bias voltage and a 50-W series resistor. The post-layout simulations of the proposed CMVD demonstrate vividly large output pulses and eye-diagrams. The chip consumes 44 mW in maximum from a 3.3-V supply and the core occupies the area of 0.1 mm².

A 6.4Gbit/s 3-Tap High-Speed IO FIR Driver with LMS Adaptation Algorithm in 65nm CMOS

Chankyu Yu, Seungwoo Shim, Taehyoun Oh — Mon, 01 Apr 2024 00:00:00 +0900

A 6.4Gb/s IO transceiver including an adaptive finite impulse response (FIR) filter has been implemented with 65nm technology. The FIR tap coefficients are adapted using sign-sign least mean square (LMS) algorithm. Eye-openings are improved under time varying conditions by creating a diverse channel loss environment. The transceiver consumes 64mW/lane at 1.2V supply and the chip size is 0.506mm^2. The measured vertical eye-opening has been improved from 152.4mV/1.06V to 356.6mV/699.3mV after pre-emphasis and the measured horizontal eye-opening is 0.484 UI at BER.

An 8G Hz SST Transmitter with Adjustable FIR and Pre-Emphasis Logic in 65nm CMOS

YIDAN ZHANG, Tae wook Kim — Mon, 01 Apr 2024 00:00:00 +0900

In response to the escalating demands for high-speed communication and the necessity for effective channel loss compensation, this study introduces an advanced transmitter (TX) system with enhanced adaptability. This system integrates a sophisticated TX architecture, augmented by a pre-emphasis logic and a three-tap Finite Impulse Response (FIR) filter, using TSMC's 65nm process technology. The core of the pre-emphasis architecture is a Voltage-Mode Driver topology, serving both as the primary driver and emphasis cell, supplemented by an additional logic to modulate the FIR's first tap. This modulation facilitates varied emphasis states, enabling tailored compensation for diverse channel losses. The FIR, realized through Current-Mode Logic (CML), optimizes power efficiency, while the driver configuration, composed of SST drivers, ensures a robust output swing. The incorporation of SST drivers ushers in a hybrid impedance control approach, merging conventional analog-loop control with impedance regulation via the SST driver slices. Simulation results show that the system achieves speeds of up to 8GHz and an output swing of 1.2V, while maintaining an eye width of 0.8 Unit Intervals (UI).

Beamforming Transmitter IC for Far-Field Wireless Charging

Seok-Jae Hur, Ji-Hun Kim, Min-su Park, Ho-won Kim, Kang-Yoon Lee — Mon, 01 Apr 2024 00:00:00 +0900

This paper introduces a Wireless Power Transfer (WPT) system tailored for far-field charging applications, leveraging beamforming technology. The system comprises a self-phase-shiftable Phase-Locked Loop (PLL) and a high-power, high-efficiency dual-band Power Amplifier (PA). The phase shift PLL is designed to operate with a reference clock frequency of 50 MHz and targets frequencies of 5.8 GHz and 4.8 GHz, specifically suited for beamforming applications, particularly in IoT devices. The PA structure is configured with two stages, incorporating interstage and output baluns for power matching. It directly amplifies the 5.8 GHz PLL output and amplifies the 4.8 GHz PLL output after dividing it by two and then amplifying the resulting 2.4 GHz signal. This system is implemented usig a 130-nm CMOS process and provides VCO gains (KVCO) of 141.72 MHz/V and 83.5 MHz/V at 5.8 GHz and 4.8 GHz, respectively. Power consumption is measured at 210mA and 120mA at a 1.2V supply voltage for 5.8 GHz and 2.4 GHz, respectively. The phase shift PLL enables a phase shift of 5.625° across the full 360° range at frequencies of 5.8 GHz and 4.8 GHz, while the PA achieves output powers of 25.41dBm and 24.48dBm, respectively.

A Proposal of Methodologies for Implementing Digital Chips in the Latest Processes

Hye-Seung Sun, In-Shin Cho — Mon, 01 Apr 2024 00:00:00 +0900

In this paper, design methodologies suitable for implementation of digital systems at various processes are suggested. Important issues about Multi Corner Multi Mode, Hierarchical Design, adoption of CCS model, and changes in design flow must be considered at ultra-fine processes. The Cortex-M0 SoC Platform is implemented with considering important issues and the results using various digital libraries are compared.

All implemented platforms meet specifications and operate normally with hardware and software. The fastest clock cycle that can be synthesized is 4ns for Samsung 28nm