Journal of Integrated Circuits and Systems

A Design Technique for Highly Parallel Pseudo-Random Ternary Sequences Generators

Jusung Park — 2025-12-31

This paper introduces a design technique and an optimized architecture for pseudo-random trit sequence (PRTS) generation and checking, aimed at high-speed serial communication systems such as PAM-3 transceivers. Unlike PRBS generators that rely on modulo-2 arithmetic, PRTS generation requires modulo-3 operations, which introduce additional design complexity. To address this, we propose a transition matrix-based framework for parallel PRTS generation, enabling efficient high-throughput sequence construction while remaining compatible with standard CMOS design methodologies. The circuits are designed in a 28-nm CMOS process using a standard-cell design flow. The generator achieves 72Gb/s operation at 1.89mW with an area of 0.00045 mm², while the checker consumes 1.64mW and occupies only 0.00218 μm². The proposed solution provides nearly a twofold improvement in both area and power efficiency when compared with a previous work.

A Duty-Cycled Continuous-Time Delta-Sigma Modulator for ExG Biopotential Acquisition

Wooyub Chun — 2025-12-31

This paper introduces a continuous-time (CT) delta-sigma analog-to-digital converter (ADC) integrated with a capacitively-coupled chopper instrumentation amplifier (CCIA) for ExG biopotential recording. The design features a duty-cycled operation that enhances power efficiency by minimizing unnecessary power dissipation during low-frequency signal acquisition. The system is optimized to meet key requirements such as low noise, low power, high input impedance, and sufficient input range for various biopotential signals. Fabricated in a standard 0.18 μm CMOS process, the ADC achieves FoMSNDR of 170.1 dB for a 10 kHz bandwidth, consuming 4.5 μW at 0.6 V. The active area is 0.138 mm².

Design and Optimization of Centimeter-Scale Long-Reach On-Chip Interconnect for Wafer-Level Computing

JiYong Park — 2025-12-31

This paper investigates two on-chip interconnect structures, a single-metal (Single M9) and a vertically stacked (M9/M8), for 100 Gb/s, 20mm links in Wafer-Level Computing (WLC) or Wafer-Scale Integration (WSI) systems, targeting an insertion loss below -15 dB at 25 GHz. Counterintuitively, 3D EM simulations reveal that the simpler single M9 channel is superior, achieving a -14.5 dB insertion loss, while the stacked structure exhibits a worse loss of -16.4 dB. This performance inversion is attributed to the dominance of dielectric loss over conductor loss in the stacked structure at high frequencies. System-level link simulations verify this finding, showing the single M9 channel achieves an open 100 Gb/s PAM-4 eye with a fixed FFE, a condition under which the stacked channel fails. This work highlights that high-frequency interconnect design involves a complex trade-off, demonstrating that a holistic analysis of both conductor and dielectric loss mechanisms is critical for achieving a truly optimal solution.

A 4 - 8GHz Analog Duty Cycle Corrector with 30-70% Correction Range for High-Speed Serial Interface

Myeongju Park — 2025-12-31

This paper presents the analog duty cycle corrector (DCC) for high-speed and accurate duty cycle correction. To enable high-speed and accurate duty cycle correction, the proposed design utilizes an integrator to extract error information as a DC voltage, while a set generator is introduced to significantly reduce lock time during initial setup time. The proposed circuit was designed using a 65-nm CMOS process. The proposed circuit supports input duty cycles ranging from 30% to 70% across a clock frequency range of 4 - 8 GHz and corrects them to 50% with an accuracy of ±0.5%. The active area of the design is 0.0053mm², with a power consumption is 4.42 mW at 8 GHz.

Design Study of a 120-GHz Amplifier on InP HEMT Technology

Junyung Cho — 2025-12-31

This paper presents the design and analysis of an amplifier operating at 120 GHz, based on a domestically developed 100 nm InP HEMT process. The maximum available gain (MAG) of three transistor types in the process was compared through simulation. Among them, the 2F20 device exhibited the most stable gain characteristics, making it suitable for high-frequency amplifier design. A single-stage common-source amplifier was fabricated, and its small-signal performance was experimentally verified. The measurement results showed a gain of approximately 3 dB and input and output return loss (|S11| and |S22|) below −4 dB in the target band, which are in good agreement with simulation results. In addition, a planar Marchand balun was designed using a single-metal-layer process. However, the measured insertion loss was significantly higher than predicted by simulation, indicating the need for further research. Finally, a differential two stage amplifier was designed and simulated, achieving a gain of 15.4 dB and a 3 dB bandwidth of 18 GHz at 120 GHz.

A Multi-Path Hybrid DC-DC Converter with Reduced Inductor Current and Wide Voltage Conversion Ratio

Jaekyun Kim — 2025-12-31

This paper presents a 5V input DC-DC converter using a proposed dual-path structure. By leveraging the benefits of a multi-path architecture, the converter reduces inductor’s DC current. The topology comprises one inductor, eight power switches, and four flying capacitors, with each path including two to three power switches in series. This structure reduces the inductor’s DC current stress, enabling the use of a compact inductor without sacrificing efficiency. The proposed converter supports a voltage conversion ratio (VCR) range of 0 to 1 and is implemented in TSMC 180nm BCD process, occupying a 3.55 mm × 2.36 mm silicon area.

A High-Efficiency Hybrid Buck-Boost Photovoltaic Energy Harvester with Adaptive Fractional Open-Circuit Voltage Maximum-Power-Point-Tracking Control

Dang Hung Phan — 2025-12-31

This paper presents an energy-efficient photovoltaic energy harvesting system achieving an ultra-wide input power (PIN) range by optimizing both maximum-power-point-tracking efficiency (ηMPPT) and power-conversion efficiency (ηCONV). An MPPT based on an adaptive fractional open-circuit voltage method is proposed to tune the fraction k based on PIN with only little power overhead, unlike other complex and power-hungry hybrid MPPTs. Also, the harvester maintains high ηCONV at low PIN levels thanks to its modified hybrid topology that operates as a buck-boost converter with three different control techniques. The proposed zero-current detection circuit reduces the control bit size and response time because it actively changes the tuning resolution according to PIN. The proposed system achieves ηMPPT >98% across a 10,000× PIN dynamic range, and the achieved ηCONV is greater than 81% across the whole range with a peak efficiency of 96.5%. Compared to other previous state-of-the-art works, this design provides the highest peak ηCONV as well as the widest PIN ranges, over which it achieves >98% ηMPPT and >80% ηCONV.

A 6-bit Digitally Controlled Vector-Sum Phase Shifter with Current Steering Architecture

Jeong Su Lee — 2025-12-31

This paper presents a 6-bit Ku-band vector-sum phase shifter (VSPS) designed for beamforming applications operating in the 10.7–12.7 GHz range. A two-stage RC polyphase filter is adopted for quadrature signal generation, achieving a maximum gain imbalance of 0.218 dB and a maximum phase error of 1.636°, outperforming RL-based alternatives in integration and broadband accuracy. The core uses a digitally controlled current-steering architecture with MOSFET-based RF cells that synthesize precise phase states via binary-weighted vector summation. This structure enables 5.625° resolution, compact layout, and low power operation. Post-layout electromagnetic(EM) simulations show RMS phase errors under 2.5°, gain errors between 0.3 to 0.5 dB, and average gain from -4.55 to -2.17 dB. With only 15.8 mW DC power consumption, the design is efficient and scalable. The proposed architecture combines high resolution, low power, and robust performance, making it well-suited for next-generation phased-array systems in Ku-band satellite communications.

Design of a 6-bit Broadband Differential Digital Attenuator Using a Hybrid Topology for DC–13 GHz Systems

Jeong Hu Nam — 2025-12-31

This paper presents the design and implementation of a 6-bit differential digital step attenuator targeting broadband transmitter applications across the DC–13 GHz range. The circuit is fabricated using a 0.13-????m SiGe BiCMOS process and achieves high-resolution attenuation with minimal insertion loss variation across 64 discrete control states. A hybrid topology is employed to optimize performance across all attenuation bits: bridged-T-type topologies are used for the 16 dB and 8 dB bits to ensure flat insertion loss in high-attenuation states; π-type topologies are adopted for the 4 dB and 2 dB bits to achieve compact layout and balanced signal paths; and MOSFET-based resistive shunt switches are utilized for the 1 dB and 0.5 dB bits, enabling fine resolution without discrete resistors. The attenuator operates in fully differential mode to match system-level signal interfaces. Simulation results confirm an RMS amplitude error below 1 dB and an RMS phase error under 16° across the DC–13 GHz frequency range. Embedded matching inductors are used to compensate for the parasitic capacitance of MOSFET switches, enhancing return loss performance. The average input and output return losses are –21.84 dB and –15.11 dB, respectively. The total chip area including pads is 1030 × 510 μm².

Dynamic Performance Enhancement of a Current-Steering DAC Using Tree-Structured Routing and Power Mesh-Based SI/PI Optimization

Inho Jang — 2025-12-31

As broadband communication systems demand increasingly higher data rates, the role of High-speed DACs has become essential. Time-Interleaved DAC (TI-DAC) architectures are widely employed to achieve higher sampling speeds by operating multiple sub-DAC channels in parallel. However, employing two sub-channels in a Time-Interleaved structure increases array area and exacerbates power integrity challenges, which can further degrade dynamic performance typically measured by SFDR. Moreover, the physical layout of each sub-DAC includes over 126-unit cells, and non-uniform routing paths between these cells can lead to dynamic mismatch in current summation, resulting in SFDR degradation. Layout-level optimization and PDN enhancement are applied, improving the SFDR from 41.5dB to 52.5dB.

Triboelectric Nanogenerator Modeling and Triboelectric Nanogenerator-Based Pressure-Sensor Interface for Implantable Total Knee Replacement

Yunchul Chung — 2025-12-31

Total knee replacement (TKR) surgeries are increasing worldwide due to the aging population and the growing activity levels of middle-aged patients. Continuous monitoring of knee-joint loading is crucial for enhancing implant design, facilitating early failure detection, and informing personalized rehabilitation. Triboelectric nanogenerators (TENGs), which convert mechanical energy into electrical energy through contact electrification and electrostatic induction, are attractive for wearable and implantable electronics owing to their high energy density and mechanical flexibility. However, implantable TENGs are often limited by small surface areas and low internal capacitance, which makes energy harvesting challenging. To address this limitation, this work employs TENGs as pressure sensors rather than energy harvesters. We present a TENG model suitable for integration into TKR implants and propose a lowpower sensor interface that rectifies and digitizes the signal using a dual-output rectifier (DOR) and a 10-bit SAR ADC. Under a 1-Hz gait-like excitation, the system measured forcedependent voltage responses and monotonic ADC outputs. These results show that the proposed TENG model and TENG sensor interface enable pressure/load monitoring in TKR implants.

A CMOS LiDAR Sensor Using Time-to-Voltage Converter for Elder-Care Applications

Somi Park — 2025-12-31

This paper presents an optoelectronic readout integrated circuit (ORIC) fabricated in 180-nm CMOS technology, tailored for high-resolution, short-range LiDAR sensing applications. The ORIC pixel integrates an on-chip P+/Nwell/Deep N-well avalanche photodiode and a CMOS transimpedance-limiting amplifier employing active feedback for low-noise performance. Then, a time-to-voltage (T2V) conversion scheme is adopted to enable precise signal quantization with minimal walk error, which is followed by a voltage-domain successive approximation register (SAR) analog-to-digital converter (ADC). This architecture is suggested to replace conventional time-to-digital converters (TDCs), thereby significantly reducing system complexity while maintaining wide dynamic range and high scalability. Post-layout simulations indicate an input dynamic range of 47.4 dB that corresponds to the detectable photocurrent levels ranging from 15 μA_pp to 3.5 mA_pp. This can be translated to a measurable distance of 31 centimeters to 4.76 meters under typical operating conditions. To the best of the authors’ knowledge, this is the first attempt to substitute a TDC with a T2V-SAR ADC pipeline for LiDAR sensors, offering a compact, low-power, and scalable solution for emerging applications such as ambient-assisted living and elderly monitoring systems.

Design Study of a 630-GHz Injection-Locked Oscillator Based on InP HBT Technology

Giyeong Nam — 2025-12-31

In this work, an injection-locked oscillator (ILO) has been designed in a 250-nm InP HBT technology for operation around 630 GHz. The ILO is based on LC cross-coupled topology with push-push structure for second harmonic extraction and fundamental signal suppression. The on-chip patch antenna is integrated to the output stage of the ILO for direct radiation into free space. The injection circuit is formed at the emitter stage of the ILO with transformer based passive balun for compact design. It will also suppress the loss that can be induced by an active circuit in the high-frequency band. The delivered output power in free-running condition is -7.6 dBm at 637.3 GHz. With an injection signal of 0 dBm at320 GHz, the delivered output power is 1 dBm at 640 GHz. Thetotal DC power consumption is 20.6 mW.