Journal of Integrated Circuits and Systems

An Energy-Efficient Multi-Channel Charge Trackable Inductor-Based Stimulation System

2025-01-01T12:37:47+09:00

The concept of "electroceuticals" has recently emerged, aiming to maximize therapeutic effects by delivering targeted electrical stimulation while minimizing side effects. To realize electroceuticals, it is essential to develop implantable stimulators that meet specific requirements, such as overcoming battery size limitations, ensuring safety, and providing effective electrical stimulation. Therefore, these stimulators must operate with high energy efficiency and have the capability to monitor the amount of charge delivered to the body. However, existing electrical stimulators fail to meet these requirements. Therefore, this study developed a Charge Trackable Inductor-Based Stimulator (CTIBS) that achieves up to 80% of peak stimulator efficiency, with a charge error between anodic and cathodic stimulation being less than 1.6%. Additionally, the number of stimulation channels has been expanded to 16, allowing flexible control over the stimulation area and density. The integrated circuit (IC) chip was designed using a 180 nm RF process, occupying an area of 5 mm².

Peripheral System for Tunneling Field-Effect Transistor-Based Content Addressable Memory

2025-01-01T12:37:59+09:00

Content Addressable Memory (CAM) is a crucial component in modern computing systems, offering rapid parallel search capabilities that significantly enhance data retrieval efficiency. CAM is increasingly employed in advanced applications such as Deep Neural Networks (DNNs), particularly within Memory-Augmented Neural Networks (MANNs) that utilize one-shot learning techniques. While CAMs can be implemented using various memory technologies such as SRAM, RRAM, and Ferroelectric FETs, this paper specifically addresses the challenges and solutions associated with TFET-based CAMs. We propose a system for TFET-based CAMs composed of four critical components: the Searchline Data Register, the Matchline Sense Amplifier, the High Voltage Switch, and the Priority Encoder. The functionality and performance of the proposed peripheral circuits have been validated through experimental testing, demonstrating the practical feasibility of integrating TFET-based CAMs into advanced circuit systems.

A 2.5 GHz, 87-fs Step, Temperature-and-Voltage-Tolerant 6-bit Digital-to-Time Converter in 28nm CMOS

2025-01-01T12:38:12+09:00

This paper presents a temperature-and-voltage-tolerant 2.5GHz 6-bit digital-to-time converter (DTC) with an 87-fs resolution. The capacitor-DAC (CDAC) based DTC can achieve high resolution and linearity, but typical DTC structures suffer from performance degradation due to temperature and voltage variations. To address this issue, we implement a replica feedback loop consisting of a regulated constant-slope DTC, which effectively maintains the delay of the DTC even as temperature and voltage conditions fluctuate. Additionally, an on-chip histogram counter accurately measures on-chip delays. The proposed DTC in this paper is fabricated in a 28-nm CMOS process, with the core occupying an area of 0.0129 mm². It operates at 2.5 GHz with a 0.9 V supply voltage, consuming only 0.82 mW. Measured results demonstrate that the full-scale range changes for 125 °C temperature variation and for 200mV supply variation are reduced by 7.2x and 1.9x, respectively.

Low-Noise EEG Sensor and Neural Stimulator : For Motion and Stimulation Artifact Removal

2025-01-01T12:38:25+09:00

This work aims to develop a neural interface system that enables electroencephalogram (EEG) measurement in wearable equipment and eliminates stimulation artifacts by processing in miniaturized neural stimulation modules. The ASIC implements a 4-channel analog-front-end (AFE) with a high input-Z buffer, 2^nd order oversampling delta-sigma ADC, stimulation noise cancellation digital processors, and digitally controlled neural stimulators into the chip. The simplified stimulation artifact rejection algorithm implemented on the digital block allows users to acquire pure neural signals while stimulating. The 3 mm x 1 mm IC chips were fabricated through the TSMC 65 nm LP process.

Reflective-Type Phase Shifter Design with a Patch Antenna for a 250 GHz On-Chip Beamforming System

2025-01-01T12:38:42+09:00

This paper introduces a reflective-type phase shifter (RTPS) and a defected ground patch antenna design for configuring a 4-bit 250 GHz on-chip beamforming system using a SiGe HBT device. The patch antenna is designed to operate at 250 GHz, with a defected ground structure implemented to address the issue of narrow bandwidth. Four ground slots, each sized 50 x 121 mm², are fabricated, and measurement results show that the patch antenna operates within the 240-257 GHz band. The RTPS is designed using a 90^o hybrid coupler and variable loads using varactors. The 90^o hybrid coupler is made compact by overlapping two adjacent 50-W quarter-wavelength lines and forming a slot on the ground plane. The varactor is based on a diode-connected SiGe HBT device, and its size is selected as the largest available 9 mm in length to maximize the capacitance variation with the bias input. Two RTPS unit cells are connected in series to achieve a 360^o phase shift, and the measurement results demonstrate a 4-bit phase shift.

An Inductor-Less 28-Gb/s NRZ Optical Receiver Analog Front-End Optimization Using BAG in 28-nm CMOS

2025-01-01T12:38:55+09:00

This paper presents an optimized design methodology for an inductor-less 28-Gb/s NRZ optical receiver (ORx) analog front-end (AFE) using the Berkeley Analog Generator (BAG) in 28-nm CMOS technology.

With the increasing demand for high-speed data transmission in optical interconnects, achieving an optimal balance between gain, bandwidth, and noise in transimpedance amplifiers (TIAs) remains challenging.

To address this challenge, optimization to maximize signal-to-noise ratio (SNR) is performed using BAG.

Measured results of the ORx AFE demonstrate an input sensitivity of 8.5-dBm average optical power at 28-Gb/s, PRBS-7.

This work highlights the potential of the BAG-based design framework for integration into advanced optical communication systems, facilitating future developments in high-speed optical inter-connects.

Design of a 520-624-GHz Amplifier-Frequency-Doubler Chain in 250-nm InP HBT Technology

2025-01-01T12:39:12+09:00

In this study, an Amplifier-Frequency-Doubler Chain (AFDC) operating around 600 GHz has been designed based on 250-nm InP HBT technology. It consists of a 300-GHz drive amplifier followed by a 600-GHz frequency doubler. The drive amplifier adopts a four-stage cascode topology, in which a staggering matching scheme is used to achieve a wide bandwidth. Additionally, to saturate the subsequent frequency doubler, load-pull matching is adopted for the output matching of the amplifier. The frequency doubler is based on a push-push topology followed by an output matching network that helps to suppress the undesired fundamental and odd-order harmonics. The integrated AFDC exhibited a simulated peak output power of -8.4 dBm, with a 3-dB bandwidth of 104 GHz (520-624 GHz), or a fractional bandwidth of 20.7% at 0-dBm input power. The simulated total DC power consumption is 282.6 mW. The layout size is 1137 X 464 mm², including probing pads.

Hardware-Software Co-Design for Analog Compute-in-Memory Accelerators Using 1-bit Sense Amplifiers

2025-01-01T12:39:31+09:00

In this paper, we present a hardware-software co-design methodology for analog compute-in-memory (CIM) accelerators with 1-bit sense amplifiers (SAs). While CIM macro using 1-bit SAs achieves high energy efficiency by eliminating multi-bit analog-to-digital converters (ADCs), it faces two key challenges: limitations in BNN layer size and the impact of SA random noise. Through neural network splitting, which divides layers into sub-blocks matching the size of the CIM macro rows, the BNN model fits the CIM macro while preserving accuracy. Additionally, the SA output probability model is obtained through measurements and replaces the binarization function of BNN, incorporating SA random noise into the BNN training process. Using these two approaches, we develop a framework to retrain BNNs tailored to the CIM accelerator and achieve 97.81% MNIST inference accuracy on the prototype 128x128 CIM accelerator fabricated in 28 nm technology.